SN74LV138AT 3 线路到 8 线路解码器/多路解复用器
The SN74LV138AT is a 3-line to 8-line decoder/demultiplexer, designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of the decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select inputs (A, B, C) and the three enable inputs (G1, G2A, G2B) select one of eight output lines. The two active-low (G2A, G2B) and one active-high (G1) enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
This device is fully specified for partial-power-down application susing Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down
| SN74LV138AT | |
| Rating | Catalog |
| Technology Family | LV-AT |
SN74LV138AT 特性
- Inputs Are TTL-Voltage Compatible
- 4.5-V to 5.5-V VCC Operation
- Max tpd of 7.6 ns at 5 V
- Typical VOLP (Output Ground Bounce)<0.8 V at VCC = 5 V, TA = 25°C
- Typical VOHV (Output VOH Undershoot)>>2.3 V at VCC = 5 V, TA = 25°C
- Support Mixed-Mode Voltage Operation on All Ports
- Ioff Supports Partial-Power Down Mode Operation
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
SN74LV138AT 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN74LV138ATD | ACTIVE | -40 to 85 | 0.21 | 1ku | SOIC (D) | 16 | 40 | TUBE | |
| SN74LV138ATDE4 | ACTIVE | -40 to 85 | 0.21 | 1ku | SOIC (D) | 16 | 40 | TUBE | |
| SN74LV138ATDG4 | ACTIVE | -40 to 85 | 0.21 | 1ku | SOIC (D) | 16 | 40 | TUBE | |
| SN74LV138ATDR | ACTIVE | -40 to 85 | 0.17 | 1ku | SOIC (D) | 16 | 2500 | LARGE T&R | |
| SN74LV138ATDRE4 | ACTIVE | -40 to 85 | 0.17 | 1ku | SOIC (D) | 16 | 2500 | LARGE T&R | |
| SN74LV138ATDRG4 | ACTIVE | -40 to 85 | 0.17 | 1ku | SOIC (D) | 16 | 2500 | LARGE T&R | |
| SN74LV138ATN | ACTIVE | -40 to 85 | 0.18 | 1ku | PDIP (N) | 16 | 25 | TUBE | |
| SN74LV138ATNE4 | ACTIVE | -40 to 85 | 0.18 | 1ku | PDIP (N) | 16 | 25 | TUBE |
SN74LV138AT 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN74LV138ATD | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV138ATD | SN74LV138ATD |
| SN74LV138ATDE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV138ATDE4 | SN74LV138ATDE4 |
| SN74LV138ATDG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV138ATDG4 | SN74LV138ATDG4 |
| SN74LV138ATDR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV138ATDR | SN74LV138ATDR |
| SN74LV138ATDRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV138ATDRE4 | SN74LV138ATDRE4 |
| SN74LV138ATDRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV138ATDRG4 | SN74LV138ATDRG4 |
| SN74LV138ATN | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74LV138ATN | SN74LV138ATN |
| SN74LV138ATNE4 | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74LV138ATNE4 | SN74LV138ATNE4 |
SN74LV138AT 应用技术支持与电子电路设计开发资源下载
- SN74LV138AT 数据资料 dataSheet 下载.PDF
- TI 德州仪器MSI 功能产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
