SN74LV4046A
The SN74LV4046A is a high-speed silicon-gate CMOS device that is pin compatible with the CD4046B and the CD74HC4046. The device is specified in compliance with JEDEC Std 7.
The SN74LV4046A is a phase-locked loop (PLL) circuit that contains a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2, and PC3). A signal input and a comparator input are common to each comparator.
The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the SN74LV4046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear operational amplifier techniques
| SN74LV4046A | |
| Rating | Catalog |
| Technology Family | LV-A |
SN74LV4046A 特性
- Choice of Three Phase Comparators
- Exclusive OR
- Edge-Triggered J-K Flip-Flop
- Edge-Triggered RS Flip-Flop
- Excellent VCO Frequency Linearity
- VCO-Inhibit Control for ON/OFF Keying and for Low Standby Power Consumption
- Optimized Power-Supply Voltage Range From 3 V to 5.5 V
- Wide Operating Temperature Range . . . -40°C to 125°C
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
SN74LV4046A 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN74LV4046AD | ACTIVE | 0 to 70 | 3.05 | 1ku | SOIC (DW) | 16 | 50 | TUBE | |
| SN74LV4046ADE4 | ACTIVE | 0 to 70 | 3.05 | 1ku | SOIC (DW) | 16 | 50 | TUBE | |
| SN74LV4046ADG4 | ACTIVE | 0 to 70 | 3.05 | 1ku | SOIC (DW) | 16 | 50 | TUBE | |
| SN74LV4046ADR | ACTIVE | 0 to 70 | 2.55 | 1ku | SOIC (DW) | 16 | 2500 | LARGE T&R | |
| SN74LV4046ADRE4 | ACTIVE | 0 to 70 | 2.55 | 1ku | SOIC (DW) | 16 | 2500 | LARGE T&R | |
| SN74LV4046ADRG4 | ACTIVE | 0 to 70 | 2.55 | 1ku | SOIC (DW) | 16 | 2500 | LARGE T&R | |
| SN74LV4046AN | ACTIVE | 0 to 70 | 2.80 | 1ku | PDIP (N) | 16 | 25 | TUBE | |
| SN74LV4046ANE4 | ACTIVE | 0 to 70 | 2.80 | 1ku | PDIP (N) | 16 | 25 | TUBE |
SN74LV4046A 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN74LV4046AD | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV4046AD | SN74LV4046AD |
| SN74LV4046ADE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV4046ADE4 | SN74LV4046ADE4 |
| SN74LV4046ADG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV4046ADG4 | SN74LV4046ADG4 |
| SN74LV4046ADR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV4046ADR | SN74LV4046ADR |
| SN74LV4046ADRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV4046ADRE4 | SN74LV4046ADRE4 |
| SN74LV4046ADRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV4046ADRG4 | SN74LV4046ADRG4 |
| SN74LV4046AN | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74LV4046AN | SN74LV4046AN |
| SN74LV4046ANE4 | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74LV4046ANE4 | SN74LV4046ANE4 |
SN74LV4046A 应用技术支持与电子电路设计开发资源下载
- SN74LV4046A 数据资料 dataSheet 下载.PDF
- TI 德州仪器特殊逻辑产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
