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SN74LV8154 具有三态输出寄存器的双路 16 位二进制计数器

The SN74LV8154 is a dual 16-bit binary counter with 3-state output registers, designed for 2-V to 5.5-V VCC operation.

This 16-bit counter (A or B) feeds a 16-bit storage register, and each storage register is further divided into an upper byte and lower byte. The GAL\, GAU\, GBL\, GBU\ inputs are used to select the byte that needs to be output at Y0-Y7. CLKA is the clock for A counter, and CLKB is the clock for B counter. RCLK is the clock for the A and B storage registers. All three clock signals are positive-edge triggered.

A 32-bit counter can be realized by connecting CLKA and CLKB together and by connecting RCOA\ to CLKBEN\.

To ensure the high-impedance state during power up or power down, GAL\, GAU\, GBL\, and GBU\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver

	SN74LV8154
Rating	Catalog
Technology Family	LV-A

SN74LV8154 特性

• Can Be Used as Two 16-Bit Counters or a Single 32-Bit Counter
• 2-V to 5.5-V VCC Operation
• Max tpd of 25 ns at 5 V (RCLK to Y)
• Typical VOLP (Output Ground Bounce)
       <0.7 V at VCC = 5 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
       >4.4 V at VCC = 5 V, TA = 25°C
• Ioff Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)

SN74LV8154 芯片订购指南

器件	状态	温度	价格	封装 | 引脚	封装数量 | 封装载体	丝印标记
SN74LV8154N	ACTIVE	0 to 70	0.35 | 1ku	PDIP (N) | 20	25 | TUBE
SN74LV8154NE4	ACTIVE	0 to 70	0.35 | 1ku	PDIP (N) | 20	25 | TUBE

SN74LV8154 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN74LV8154N	Pb-Free (RoHS)	CU NIPDAU	N/A for Pkg Type	SN74LV8154N	SN74LV8154N
SN74LV8154NE4	Pb-Free (RoHS)	CU NIPDAU	N/A for Pkg Type	SN74LV8154NE4	SN74LV8154NE4

SN74LV8154 应用技术支持与电子电路设计开发资源下载

1. SN74LV8154 数据资料 dataSheet 下载.PDF
2. TI 德州仪器MSI 功能产品选型与价格 . xls
3. Logic Guide 2009 (PDF 4263 KB)
4. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
5. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
6. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
7. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
8. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
9. Designing With Logic (PDF 186 KB)
10. Live Insertion (PDF 150 KB)
11. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
12. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
13. HiRel Unitrode Power Management Brochure (PDF 206 KB)
14. LOGIC Pocket Data Book (PDF 6001 KB)
15. HiRel Unitrode Power Management Brochure (PDF 206 KB)
16. Logic Cross-Reference (PDF 2938 KB)