SN74LVT8980A-EP 增强型产品嵌入式测试总线控制器 Ieee Std 1149.1 (Jtag) Tap 主控制器
The SN74LVT8980A embedded test-bus controllers (eTBCs) are members of the TI broad family of testability integrated circuits. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit assemblies. Unlike most other devices of this family, the eTBCs are not boundary-scannable devices; rather, their function is to master an IEEE Std 1149.1 (JTAG) test access port (TAP) under the command of an embedded host microprocessor/microcontroller. Thus, the eTBCs enable the practical and effective use of the IEEE Std 1149.1 test-access infrastructure to support embedded/built-in test, emulation, and configuration/maintenance facilities at board and system levels.
The eTBCs master all TAP signals required to support one 4- or 5-wire IEEE Std 1149
|
SN74LVT8980A-EP |
| Voltage Nodes(V) |
3.3, 2.7 |
| Vcc range(V) |
2.7 to 3.6 |
| Input Level |
TTL/CMOS |
| Output Level |
LVTTL |
| Rating |
HiRel Enhanced Product |
| Technology Family |
JTAG |
SN74LVT8980A-EP 特性
- Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product-Change Notification
- Qualification Pedigree
- Members of Texas Instruments Broad Family of Testability Products Supporting IEEE Std 1149.1-1990 (JTAG) Test Access Port (TAP) and Boundary-Scan Architecture
- Provide Built-In Access to IEEE Std 1149.1 Scan-Accessible Test/Maintenance Facilities at Board and System Levels
- While Powered at 3.3 V, the TAP Interface Is Fully 5-V Tolerant for Mastering Both 5-V and/or 3.3-V IEEE Std 1149.1 Targets
- Simple Interface to Low-Cost 3.3-V Microprocessors/Microcontrollers Via 8-Bit Asynchronous Read/Write Data Bus
- Easy Programming Via Scan-Level Command Set and Smart TAP Control
- Transparently Generate Protocols to Support Multidrop TAP Configurations Using TI’s Addressable Scan Port
- Flexible TCK Generator Provides Programmable Division, Gated-TCK, and Free-Running-TCK Modes
- Discrete TAP Control Mode Supports Arbitrary TMS/TDI Sequences for Noncompliant Targets
- Programmable 32-Bit Test Cycle Counter Allows Virtually Unlimited Scan/Test Length
- Accommodate Target Retiming (Pipeline) Delays of up to 15 TCK Cycles
- Test Output Enable (TOE)\ Allows for External Control of TAP Signals
- High-Drive Outputs (–32-mA IOH, 64-mA IOL) at TAP Support Backplane Interface and/or High Fanout
SN74LVT8980A-EP 芯片订购指南
| 器件 |
状态 |
温度 |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| SN74LVT8980AIDWREP |
ACTIVE |
-40 to 85 |
8.14 | 1ku |
SOIC(DW) | 24 |
2000 | LARGE T&R |
|
| V62/03668-01XE |
ACTIVE |
-40 to 85 |
8.14 | 1ku |
SOIC(DW) | 24 |
2000 | LARGE T&R |
|
SN74LVT8980A-EP 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| SN74LVT8980AIDWREP |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN74LVT8980AIDWREP |
SN74LVT8980AIDWREP |
| V62/03668-01XE |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
V62/03668-01XE |
V62/03668-01XE |
SN74LVT8980A-EP 应用技术支持与电子电路设计开发资源下载
- SN74LVT8980A-EP 数据资料 dataSheet 下载.PDF
- TI 德州仪器特殊逻辑产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
