These octal transceivers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
The ’LVTH543 devices contain two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (LEAB\ or LEBA\) and output-enable (OEAB\ or OEBA\) inputs are provided for each register, to permit independent control in either direction of data flow.
The A-to-B enable (CEAB)\ input must be low to enter data from A or to output data from B. If CEAB\ is low and LEAB\ is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB\ puts the A latches in the storage mode. With CEAB\ and OEAB\ both low, the 3-state B outputs are active and reflect the data present at the output of the A latches
| SN74LVTH543 | |
| Voltage Nodes(V) | 3.3, 2.7 |
| Vcc range(V) | 2.7 to 3.6 |
| Input Level | TTL/CMOS |
| Output Level | LVTTL |
| Output Drive(mA) | -32/+64 |
| No. of Bits | 8 |
| Logic | True |
| Technology Family | LVT |
| Rating | Catalog |
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN74LVTH543DW | ACTIVE | -40 to 85 | 1.15 | 1ku | SOIC (DW) | 24 | 25 | TUBE | |
| SN74LVTH543DWE4 | ACTIVE | -40 to 85 | 1.15 | 1ku | SOIC (DW) | 24 | 25 | TUBE | |
| SN74LVTH543DWG4 | ACTIVE | -40 to 85 | 1.15 | 1ku | SOIC (DW) | 24 | 25 | TUBE |
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN74LVTH543DW | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LVTH543DW | SN74LVTH543DW |
| SN74LVTH543DWE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LVTH543DWE4 | SN74LVTH543DWE4 |
| SN74LVTH543DWG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LVTH543DWG4 | SN74LVTH543DWG4 |
