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SN74SSTV16859 具有 SSTL_2 输入和输出的 13 位至 26 位寄存缓冲器

This 13-bit to 26-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.

All inputs are SSTL_2, except the LVCMOS reset (RESET)\ input. All outputs are SSTL_2, Class II compatible.

The SN74SSTV16859 operates from a differential clock (CLK and CLK\). Data are registered at the crossing of CLK going high and CLK\ going low.

The device supports low-power standby operation. When RESET\ is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET\ is low, all registers are reset and all outputs are forced low. The LVCMOS RESET\ input always must be held at a valid logic high or low level.

To ensure defined outputs from the register before a stable clock has been supplied, RESET\ must be held in the low state during power up

	SN74SSTV16859
Voltage Nodes(V)	2.5
Input Level	SSTL_2
Output Level	SSTL_2
Technology Family	SSTV
Rating	Catalog

SN74SSTV16859 特性

• Member of the Texas Instruments Widebus™ Family
• 1-to-2 Outputs to Support Stacked DDR DIMMs
• Supports SSTL_2 Data Inputs
• Outputs Meet SSTL_2 Class II Specifications
• Differential Clock (CLK and CLK\) Inputs
• Supports LVCMOS Switching Levels on the RESET\ Input
• RESET\ Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low
• Pinout Optimizes DIMM PCB Layout
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)

SN74SSTV16859 芯片订购指南

器件	状态	温度	价格（美元）	封装 | 引脚	封装数量 | 封装载体	丝印标记
74SSTV16859DGGRG4	ACTIVE	0 to 70	2.75 | 1ku	TSSOP (DGG) | 64	2000 | LARGE T&R
74SSTV16859RGQ8G3	ACTIVE	0 to 70	2.75 | 1ku	VQFN (RGQ) | 56	2000 | LARGE T&R
SN74SSTV16859DGG	OBSOLETE			TSSOP (DGG) | 64
SN74SSTV16859DGGG4	OBSOLETE			TSSOP (DGG) | 64
SN74SSTV16859DGGR	ACTIVE	0 to 70	2.75 | 1ku	TSSOP (DGG) | 64	2000 | LARGE T&R
SN74SSTV16859RGQ8	ACTIVE	0 to 70	2.75 | 1ku	VQFN (RGQ) | 56	2000 | LARGE T&R
SN74SSTV16859RGQR	ACTIVE	0 to 70	2.75 | 1ku	VQFN (RGQ) | 56	2000 | LARGE T&R

SN74SSTV16859 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
74SSTV16859DGGRG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-2-260C-1 YEAR	74SSTV16859DGGRG4	74SSTV16859DGGRG4
74SSTV16859RGQ8G3	Green (RoHS & no Sb/Br)	CU SN	Level-3-260C-168 HR	74SSTV16859RGQ8G3	74SSTV16859RGQ8G3
SN74SSTV16859DGGR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-2-260C-1 YEAR	SN74SSTV16859DGGR	SN74SSTV16859DGGR
SN74SSTV16859RGQ8	Green (RoHS & no Sb/Br)	CU SN	Level-3-260C-168 HR	SN74SSTV16859RGQ8	SN74SSTV16859RGQ8
SN74SSTV16859RGQR	TBD	CU SNPB	Level-3-235C-168 HR	SN74SSTV16859RGQR	SN74SSTV16859RGQR

SN74SSTV16859 应用技术支持与电子电路设计开发资源下载

1. SN74SSTV16859 数据资料 dataSheet 下载.PDF
2. TI 德州仪器特殊逻辑产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)