SN74V245 4096 x 18 同步 FIFO 存储器
The SN74V215, SN74V225, SN74V235, and SN74V245 are very high-speed, low-power CMOS clocked first-in first-out (FIFO) memories. They support clock frequencies up to 133 MHz and have read-access times as fast as 5 ns. These DSP-Sync™ FIFO memories feature read and write controls for use in applications such as DSP-to-processor communication, DSP-to-analog front end (AFE) buffering, network, video, and data communications.
These are synchronous FIFOs, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident
|
SN74V215 |
SN74V225 |
SN74V235 |
SN74V245 |
| Depth |
512 |
1024 |
2048 |
4096 |
| Width |
18 |
18 |
18 |
18 |
| Fmax(MHz) |
133 |
133 |
133 |
133 |
| Sync/Async |
S |
S |
S |
S |
| Voltage Nodes(V) |
3.3 |
3.3 |
3.3 |
3.3 |
| Vcc range(V) |
3.0 to 3.6 |
3.0 to 3.6 |
3.0 to 3.6 |
3.0 to 3.6 |
| Technology Family |
V |
V |
V |
V |
| Output Drive(mA) |
-2/8 |
-2/8 |
-2/8 |
-2/8 |
| Rating |
Catalog |
Catalog |
Catalog |
Catalog |
SN74V245 特性
- 512 × 18-Bit Organization Array (SN74V215)
- 1024 × 18-Bit Organization Array (SN74V225)
- 2048 × 18-Bit Organization Array (SN74V235)
- 4096 × 18-Bit Organization Array (SN74V245)
- 7.5-ns Read/Write Cycle Time
- 3.3-V VCC, 5-V Input Tolerant
- First-Word or Standard Fall-Through Timing
- Single or Double Register-Buffered Empty and Full Flags
- Easily Expandable in Depth and Width
- Asynchronous or Coincident Read and Write Clocks
- Asynchronous or Synchronous Programmable Almost-Empty and Almost-Full Flags With Default Settings
- Half-Full Flag Capability
- Output Enable Puts Output Data Bus in High-Impedance State
- High-Performance Submicron CMOS Technology
- Packaged in 64-Pin Thin Quad Flat Package
- DSP and Microprocessor Interface Control Logic
- Provide a DSP Glueless Interface to Texas Instruments TMS320™ DSPs
SN74V245 芯片订购指南
| 器件 |
状态 |
温度 |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| SN74V245-10PAG |
ACTIVE |
0 to 70 |
9.49 | 1ku |
TQFP (PAG) | 64 |
160 | JEDEC TRAY (10+1) |
|
| SN74V245-15PAG |
ACTIVE |
0 to 70 |
13.42 | 1ku |
TQFP (PAG) | 64 |
160 | JEDEC TRAY (10+1) |
|
| SN74V245-20PAG |
ACTIVE |
0 to 70 |
4.16 | 1ku |
TQFP (PAG) | 64 |
160 | JEDEC TRAY (10+1) |
|
| SN74V245-7PAG |
ACTIVE |
0 to 70 |
13.07 | 1ku |
TQFP (PAG) | 64 |
160 | JEDEC TRAY (10+1) |
|
SN74V245 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| CV215-10PAGG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-3-260C-168 HR |
CV215-10PAGG4 |
CV215-10PAGG4 |
| SN74V245-10PAG |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-3-260C-168 HR |
SN74V245-10PAG |
SN74V245-10PAG |
| SN74V245-15PAG |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-3-260C-168 HR |
SN74V245-15PAG |
SN74V245-15PAG |
| SN74V245-20PAG |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-3-260C-168 HR |
SN74V245-20PAG |
SN74V245-20PAG |
| SN74V245-7PAG |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-3-260C-168 HR |
SN74V245-7PAG |
SN74V245-7PAG |
SN74V245 应用技术支持与电子电路设计开发资源下载
- SN74V245 数据资料 dataSheet 下载.PDF
- TI 德州仪器特殊逻辑产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
