CD40103B-MIL CMOS 8 级可预置 8 位二进制同步递减计数器
CD40102B, and CD40103B consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The CD40102B is configured as two cascaded 4-bit BCD counters, and the CD40103B contains a single 8-bit binary counter. Each type has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the CARRY-OUT/ZERO-DEFECT output are active-low logic.
In normal operation, the counter is decremented by one count on each positive transition of the CLOCK. Counting is inhibited when the CARRY-IN/COUNTER ENABLE (CI/CE)\ input is high. The CARRY-OUT/ZERO-DEFECT (CO/ZD)\ output goes low when the count reaches zero if the CI/CE\ input is low, and remains low for one full clock period
|
CD40103B-MIL |
| Voltage Nodes(V) |
5, 10, 15 |
| Vcc range(V) |
3.0 to 18.0 |
| Input Level |
CMOS |
| Output Level |
CMOS |
| Output Drive(mA) |
-3.2/1 |
| Rating |
Military |
| Technology Family |
CD4000 |
CD40103B-MIL 特性
- Synchronous or asynchronous preset
- Medium-speed operation: fCL = 3.6 MHz (typ.) @ VDD = 10V
- Cascadable
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (full package-temperature range) =
1 V at VDD = 5 V
2 V at VDD = 10 V
2.5 V at VDD = 15 V
- Standardized, symmetrical output characteristics
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
- Applications:
- Divide-by-"N" counters
- Programmable timers
- Interrupt timers
- Cycle/program counter
CD40102B - 2-Decade BCD Type
CD40103B - 8-Bit Binary Type
CD40103B-MIL 芯片订购指南
| 器件 |
状态 |
温度 |
价格 |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| CD40103BF |
ACTIVE |
-55 to 125 |
5.36 | 1ku |
CDIP (J) | 16 |
1 | TUBE |
|
| CD40103BF3A |
ACTIVE |
-55 to 125 |
6.27 | 1ku |
CDIP (J) | 16 |
1 | TUBE |
|
CD40103B-MIL 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| CD40103BF |
TBD |
A42 |
N/A for Pkg Type |
CD40103BF |
CD40103BF |
| CD40103BF3A |
TBD |
A42 |
N/A for Pkg Type |
CD40103BF3A |
CD40103BF3A |
CD40103B-MIL 应用技术支持与电子电路设计开发资源下载
- CD40103B-MIL 数据资料 dataSheet 下载.PDF
- TI 德州仪器MSI 功能产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
