CD4066B-Q1 CMOS 四路双向开关
The CD4066B-Q1 is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin-for-pin compatible with the CD4016B, but exhibits a much lower on-state resistance. In addition, the on-state resistance is relatively constant over the full signal-input range.
The CD4066B-Q1 consists of four bilateral switches, each with independent controls. Both the p and the n devices in a given switch are biased on or off simultaneously by the control signal. As shown in , the well of the n-channel device on each switch is tied to either the input (when the switch is on) or to VSS (when the switch is off). This configuration eliminates the variation of the switch-transistor threshold voltage with input signal and, thus, keeps the on-state resistance low over the full operating-signal range
|
CD4066B-Q1 |
| Configuration |
4 X SPST (NO) |
| ron(max)(ohms) |
240 |
| Technology Family |
CD4000 |
| Voltage Nodes(V) |
5,10,15 |
| IL OFF(Max)(nA) |
+/-1000 |
| RON Mis-match(Max)(Ohms) |
5 |
| ON Time(Max)(ns) |
30 |
| OFF Time(Max)(ns) |
30 |
| Rating |
Automotive |
| VCC(Min)(V) |
3 |
| VCC(Max)(V) |
18 |
| Pin/Package |
14SOIC |
| Operating Temperature Range(°C) |
-40 to 125 |
CD4066B-Q1 特性
- Qualified for Automotive Applications
- 15-V Digital or ±7.5-V Peak-to-Peak Switching
- 125-Ω Typical On-State Resistance for 15-V Operation
- Switch On-State Resistance Matched to Within 5 Ω Over 15-V Signal-Input Range
- On-State Resistance Flat Over Full Peak-to-Peak Signal Range
- High On/Off Output-Voltage Ratio: 80 dB Typical at fis = 10 kHz, RL = 1 kύ
- High Degree of Linearity: <0.5% Distortion Typical at fis = 1 kHz, Vis = 5 V p-p,
VDD – VSS ≥ 10 V, RL = 10 kΩ
- Extremely Low Off-State Switch Leakage, Resulting in Very Low Offset Current
and High Effective Off-State Resistance: 10 pA Typical at VDD – VSS = 10 V,
TA = 25°C
- Extremely High Control Input Impedance (Control Circuit Isolated From Signal Circuit):
1012 Ω Typical
- Low Crosstalk Between Switches: –50 dB Typical at fis = 8 MHz, RL = 1 kΩ
- Matched Control-Input to Signal-Output Capacitance: Reduces Output Signal Transients
- Frequency Response, Switch On = 40 MHz Typical
- 100% Tested for Quiescent Current at 20 V
- 5-V, 10-V, and 15-V Parametric Ratings
- Latch-Up Exceeds 100mA per JESD78 - Class I
- Meets All Requirements of JEDEC Tentative Standard No. 13-B, Standard Specifications for Description of "B" Series CMOS Devices
- APPLICATIONS
- Analog Signal Switching/Multiplexing: Signal Gating, Modulator, Squelch Control,
Demodulator, Chopper, Commutating Switch
- Digital Signal Switching/Multiplexing
- Transmission-Gate Logic Implementation
CD4066B-Q1 芯片订购指南
| 器件 |
状态 |
温度 |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| CD4066BQDRQ1 |
PREVIEW |
-40 to 125 |
SOIC (D) | 14 |
2500 | LARGE T&R |
|
CD4066B-Q1 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| CD4066BQDRQ1 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD4066BQDRQ1 |
CD4066BQDRQ1 |
CD4066B-Q1 应用技术支持与电子电路设计开发资源下载
- CD4066B-Q1 数据资料 dataSheet 下载.PDF
- TI 德州仪器信号开关产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- 防止模拟开关的额外功耗 (PDF 392 KB) (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
