CD4072B-MIL CMOS 双路 4 输入或门
CD4071B, CD4072B and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates.
The CD4071B, CD4072B, and CD4075B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes) and 14-lead thin shrink small-outline packages (PW and PWR suffixes).
|
CD4072B-MIL |
| Voltage Nodes(V) |
5, 10, 15 |
| Rating |
Catalog |
| Technology Family |
CD4000 |
CD4072B-MIL 特性
- Medium-Speed Operation - tPLH, tPHL = 60 ns (typ.) at VDD = 10 V
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Standardized, symmetrical output characteristics
- Noise margin (full package-temperature range):
1 V at VDD = 5 V
2 V at VDD = 10 V
2.5 V at VDD = 15 V
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
CD4072B-MIL 芯片订购指南
| 器件 |
状态 |
温度 |
价格 |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| 7706002CA |
ACTIVE |
-55 to 125 |
4.59 | 1ku |
CDIP (J) | 14 |
1 | TUBE |
|
| CD4072BF |
ACTIVE |
-55 to 125 |
3.92 | 1ku |
CDIP (J) | 14 |
1 | TUBE |
|
| CD4072BF3A |
ACTIVE |
-55 to 125 |
4.59 | 1ku |
CDIP (J) | 14 |
1 | TUBE |
|
CD4072B-MIL 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| 7706002CA |
TBD |
A42 |
N/A for Pkg Type |
7706002CA |
7706002CA |
| CD4072BF |
TBD |
A42 |
N/A for Pkg Type |
CD4072BF |
CD4072BF |
| CD4072BF3A |
TBD |
A42 |
N/A for Pkg Type |
CD4072BF3A |
CD4072BF3A |
CD4072B-MIL 应用技术支持与电子电路设计开发资源下载
- CD4072B-MIL 数据资料 dataSheet 下载.PDF
- TI 德州仪器门电路产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
