CD4520B CMOS 双路二进制加计数器
CD4518 Dual BCD Up-Counter and CD4520 Dual Binary Up-Counter each consist of two identical, internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or negative-going transition. For single-unit operation the ENABLE input is maintained high and the counter advances on each positive-going transition of the CLOCK. The counters are cleared by high levels on their RESET lines.
The counter can be cascaded in the ripple mode by connecting Q4 to the enable input of the subsequent counter while the CLOCK input of the latter is held low.
The CD4518B and CD4520B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
| CD4520B | |
| Voltage Nodes(V) | 5, 10, 15 |
| Vcc range(V) | 3.0 to 18.0 |
| Input Level | CMOS |
| Output Level | CMOS |
| Rating | Catalog |
| Technology Family | CD4000 |
CD4520B 特性
- Medium-speed operation - 6-MHz typical clock frequency at 10 V
- Positive- or negative-edge triggering
- Synchronous internal carry propagation
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (over full package-temperature range):
- 1 V at VDD = 5 V
- 2 V at VDD = 10 V
- 2.5 V at VDD = 15 V
- 5-V, 10-V, and 15-V parametric ratings
- Standardized, symmetrical output characteristics
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
- Applications
- Multistage synchronous counting
- Multistage ripple counting
- Frequency dividers
CD4520B 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| CD4520BE | ACTIVE | -55 to 125 | 1.20 | 1ku | PDIP (N) | 16 | 25 | TUBE | |
| CD4520BEE4 | ACTIVE | -55 to 125 | 1.20 | 1ku | PDIP (N) | 16 | 25 | TUBE | |
| CD4520BNSR | ACTIVE | -55 to 125 | 1.15 | 1ku | SO (NS) | 16 | 2000 | LARGE T&R | |
| CD4520BNSRE4 | ACTIVE | -55 to 125 | 1.15 | 1ku | SO (NS) | 16 | 2000 | LARGE T&R | |
| CD4520BNSRG4 | ACTIVE | -55 to 125 | 1.15 | 1ku | SO (NS) | 16 | 2000 | LARGE T&R | |
| CD4520BPW | ACTIVE | -55 to 125 | 1.20 | 1ku | TSSOP (PW) | 16 | 90 | TUBE | |
| CD4520BPWE4 | ACTIVE | -55 to 125 | 1.20 | 1ku | TSSOP (PW) | 16 | 90 | TUBE | |
| CD4520BPWG4 | ACTIVE | -55 to 125 | 1.20 | 1ku | TSSOP (PW) | 16 | 90 | TUBE |
CD4520B 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| CD4520BE | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | CD4520BE | CD4520BE |
| CD4520BEE4 | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | CD4520BEE4 | CD4520BEE4 |
| CD4520BNSR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | CD4520BNSR | CD4520BNSR |
| CD4520BNSRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | CD4520BNSRE4 | CD4520BNSRE4 |
| CD4520BNSRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | CD4520BNSRG4 | CD4520BNSRG4 |
| CD4520BPW | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | CD4520BPW | CD4520BPW |
| CD4520BPWE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | CD4520BPWE4 | CD4520BPWE4 |
| CD4520BPWG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | CD4520BPWG4 | CD4520BPWG4 |
CD4520B 应用技术支持与电子电路设计开发资源下载
- CD4520B 数据资料 dataSheet 下载.PDF
- TI 德州仪器MSI 功能产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
