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CD4556B-MIL 输出可选高电压的 CMOS 双路二进制 4 选 1 解码器/多路解复用器

CD4555B and CD4556B are dual one-of-four decoders/demultiplexers. Each decoder has two select inputs (A and B), an Enable input (E\), and four mutually exclusive outputs. On the CD4555B the outputs are high on select; on the CD4556B the outputs are low on select.

When the enable input is high, the outputs of the CD4555B remain low and the outputs of the CD4556B remain high regardless of the state of the select inputs A and B. The CD4555B and CD4556B are similar to types MC14555 and MC14556, respectively.

The CD4555B and CD4556B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastics packages (E suffix), and 16-lead small-outline packages (M, M96, and MT suffixes).

	CD4556B-MIL
Voltage Nodes(V)	5, 10, 15
Rating	Catalog
Technology Family	CD4000

CD4556B-MIL 特性

• Expandable with multiple packages
• Standard, symmetrical output characteristics
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 µA at 18 V over full package temperature range; 100 na at 18 V and 25°C
• Noise margin (full package-temperature range):
        1 V at VDD = 5 V
        2 V at VDD = 10 V
        2.5 V at VDD = 15 V
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
• Applications:
  • Decoding
  • Code conversion
  • Demultiplexing (using Enable input as a data input)
  • Memory chip-enable selection
  • Function selection

CD4556B-MIL 芯片订购指南

器件	状态	温度	价格	封装 | 引脚	封装数量 | 封装载体	丝印标记
CD4556BF	ACTIVE	-55 to 125	5.45 | 1ku	CDIP (J) | 16	1 | TUBE
CD4556BF3A	ACTIVE	-55 to 125	5.45 | 1ku	CDIP (J) | 16	1 | TUBE

CD4556B-MIL 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
CD4556BF	TBD	A42	N/A for Pkg Type	CD4556BF	CD4556BF
CD4556BF3A	TBD	A42	N/A for Pkg Type	CD4556BF3A	CD4556BF3A

CD4556B-MIL 应用技术支持与电子电路设计开发资源下载

1. CD4556B-MIL 数据资料 dataSheet 下载.PDF
2. TI 德州仪器MSI 功能产品选型与价格 . xls
3. Logic Guide 2009 (PDF 4263 KB)
4. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
5. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
6. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
7. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
8. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
9. Designing With Logic (PDF 186 KB)
10. Live Insertion (PDF 150 KB)
11. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
12. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
13. HiRel Unitrode Power Management Brochure (PDF 206 KB)
14. LOGIC Pocket Data Book (PDF 6001 KB)
15. HiRel Unitrode Power Management Brochure (PDF 206 KB)
16. Logic Cross-Reference (PDF 2938 KB)