OMAP3530-HIREL OMAP3530-HiRel 和 OMAP3525-HiRel 应用处理器
OMAP3525 and OMAP3530 high-performance, applications processors are based on the enhanced OMAP™ 3 architecture.
The OMAP™ 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following:
- Streaming video
- 3D mobile gaming
- Video conferencing
- High-resolution still image
The device supports high-level operating systems (OSs), such as:
This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products.
The following subsystems are part of the device:
- Microprocessor unit (MPU) subsystem based on the ARM Cortex™-A8 microprocessor
- IVA2
|
OMAP3530-HIREL |
USB |
2 |
MMC/SD |
3 |
UART (SCI) |
3 |
I2C |
3 |
McBSP |
5 |
DMA (Ch) |
64-Ch EDMA,32-Bit Channel SDMA |
Video Port (Configurable) |
1 Dedicated Output,1 Dedicated Input |
IO Supply (V) |
1.8,3.0 (MMC1 Only) |
Operating Temperature Range (C) |
-40 to 105,0 to 90 |
Pin/Package |
515POP-FCBGA |
OMAP3530-HIREL 特性
- OMAP325 and OMAP3530 Applications Processor:
- OMAP™ 3 Architecture
- MPU Subsystem
- Up to 600-MHz ARM Cortex™-A8 Core
- NEON™ SIMD Coprocessor
- High Performance Image, Video, Audio (IVA2.2™) Accelerator Subsystem
- Up to 520-MHz TMS320C64x+™ DSP Core
- Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels)
- Video Hardware Accelerators
- POWERVR SGX™ Graphics Accelerator (OMAP3530 Device Only)
- Tile Based Architecture Delivering up to 10 MPoly/sec
- Universal Scalable Shader Engine: Multi-threaded Engine Incorporating
Pixel and Vertex Shader Functionality
- Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0
- Fine Grained Task Switching, Load Balancing, and Power Management
- Programmable High Quality Image Anti-Aliasing
- Fully Software-Compatible With C64x and C64x and ARM9™
- Commercial and Extended Temperature Grades
- Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
- Eight Highly Independent Functional Units
- +Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit,
or Quad 8-Bit Arithmetic per Clock Cycle
OMAP3530-HIREL 芯片订购指南
器件 |
状态 |
温度 |
价格(美元) |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
OMAP3530DZCBB |
ACTIVE |
0 to 90 |
80.58 | 1ku |
POP-FCBGA (CBB) | 515 |
168 | JEDEC TRAY (5+1) |
|
OMAP3530DZCBBA |
ACTIVE |
-40 to 105 |
82.88 | 1ku |
POP-FCBGA (CBB) | 515 |
168 | JEDEC TRAY (5+1) |
|
OMAP3530-HIREL 质量与无铅数据
器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
OMAP3530DZCBB |
Green (RoHS & no Sb/Br) |
SNAGCU |
Level-3-260C-168 HR |
OMAP3530DZCBB |
OMAP3530DZCBB |
OMAP3530DZCBBA |
Green (RoHS & no Sb/Br) |
SNAGCU |
Level-3-260C-168 HR |
OMAP3530DZCBBA |
OMAP3530DZCBBA |
OMAP3530-HIREL 应用技术支持与电子电路设计开发资源下载
- OMAP3530-HIREL 数据资料 dataSheet 下载.PDF
- TI 德州仪器DaVinci™ 数字媒体处理器选型与价格 . xls