SE555-SP QML V 类精密定时器

The SE555 is a precision timing circuit capable of producing accurate time delays or oscillation. In the time-delay or monostable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the astable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor.

The threshold and trigger levels normally are two-thirds and one-third, respectively, of VCC. These levels can be altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can override all other inputs and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground.

The output circuit is capable of sinking or sourcing current up to 100 mA. Operation is specified for supplies of 4.5 V to 16.5 V. With a 5-V supply, output levels are compatible with TTL inputs

SE555-SP
VCC (Min) (V) 4.5    
VCC (Max) (V) 16.5    
Operating Temperature Range (C) -55 to 125
Pin/Package 8CDIP
SE555-SP 特性
SE555-SP 芯片订购指南
器件 状态 温度 (oC) 价格(美元) 封装 | 引脚 封装数量 | 封装载体 丝印标记
5962-9855501VPA ACTIVE -55 to 125 205.50 | 100u CDIP (JG) | 8 1 | TUBE  
SE555-SP 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
5962-9855501VPA TBD   A42   N/A for Pkg Type 5962-9855501VPA 5962-9855501VPA
SE555-SP 应用技术支持与电子电路设计开发资源下载
  1. SE555-SP 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器时钟与计时器选型与价格参考 . xls
SE555-SP 工具与软件
名称 型号 公司 工具/软件类型
音频的快速搜索选择工具 AUDIO_SELECTION_TOOL Texas Instruments 实用程序/插件