SN10KHT5541 具有三态输出的八路 ECL 至 TTL 转换器
This octal ECL-to-TTL translator is designed to provide a efficient translation between a 10KH ECL signal environment and a TTL signal environment. This device is designed specifically to improve the performance and density of ECL-to-TTL CPU/bus-oriented functions such as memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.
Two output-enable pins, OE1 and OE2, are provided. These control inputs are ANDed together with OE1 being ECL compatible and OE2 being TTL compatible. This offers the choice of controlling the outputs of the device from either a TTL or ECL signal environment.
The SN10KHT5541 is characterized for operation from 0°C to 75°C
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SN10KHT5541 特性
- 10KH Compatible
- ECL and TTL Control Inputs
- Noninverting Outputs
- Flow-Through Architecture Optimizes PCB Layout
- Center Pin VCC, VEE, and GND Configurations Minimize High-Speed Switching Noise
- Package Options Include "Small Outline" Packages and Standard Plastic 300-mil DIPs
SN10KHT5541 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN10KHT5541DW | ACTIVE | 0 to 70 | 11.40 | 1ku | SOIC (DW) | 24 | 25 | TUBE | |
| SN10KHT5541NT | ACTIVE | 0 to 70 | 10.80 | 1ku | PDIP (NT) | 24 | 15 | TUBE | |
| SN10KHT5541NTE4 | ACTIVE | 0 to 70 | 10.80 | 1ku | PDIP (NT) | 24 | 15 | TUBE |
SN10KHT5541 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN10KHT5541DW | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN10KHT5541DW | SN10KHT5541DW |
| SN10KHT5541NT | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN10KHT5541NT | SN10KHT5541NT |
| SN10KHT5541NTE4 | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN10KHT5541NTE4 | SN10KHT5541NTE4 |
SN10KHT5541 应用技术支持与电子电路设计开发资源下载
- SN10KHT5541 数据资料 dataSheet 下载.PDF
- TI 德州仪器电压电平转换产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
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- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
