SN10KHT5574 具有 D 类边沿触发器和三态输出的八路 ECL 至 TTL 转换器
This octal ECL-to-TTL translator is designed to provide efficient translation between a 10KH ECL signal environment and a TTL signal environment. This device is designed specifically to improve the performance and density of ECL-to-TTL CPU/bus-oriented functions such as memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.
The eight flip-flops of the SN10KHT5574 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic levels that were set up at the D inputs.
A buffered output-enable input (OE) can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly
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| Voltage Nodes(V) | |
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SN10KHT5574 特性
- 10KH Compatible
- ECL Clock and TTL Control Inputs
- Flow-Through Architecture Optimizes PCB Layout
- Center Pin VCC, VEE, and GND Configurations Minimize High-Speed Switching Noise
- Package Options Include "Small Outline" Packages and Standard Plastic DIPs
SN10KHT5574 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN10KHT5574DW | ACTIVE | 0 to 70 | 11.40 | 1ku | SOIC (DW) | 24 | 25 | TUBE | |
| SN10KHT5574NT | ACTIVE | 0 to 70 | 10.80 | 1ku | PDIP (NT) | 24 | 15 | TUBE | |
| SN10KHT5574NTE4 | ACTIVE | 0 to 70 | 10.80 | 1ku | PDIP (NT) | 24 | 15 | TUBE |
SN10KHT5574 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN10KHT5574DW | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN10KHT5574DW | SN10KHT5574DW |
| SN10KHT5574NT | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN10KHT5574NT | SN10KHT5574NT |
| SN10KHT5574NTE4 | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN10KHT5574NTE4 | SN10KHT5574NTE4 |
SN10KHT5574 应用技术支持与电子电路设计开发资源下载
- SN10KHT5574 数据资料 dataSheet 下载.PDF
- TI 德州仪器电压电平转换产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
