SN65EPT22 3.3V 双路 LVTTL/LVCMOS 至差动 LVPECL 缓冲器
SN65EPT22
Signaling Rate(Mbps)
4000
Input Signal
LVTTL,CMOS
Output Signal
LVPECL
No. of Rx
2
No. of Tx
2
Supply Voltage(s)(V)
3.3
ICC(Max)(mA)
50
Rx tpd(Typ)(ns)
0.55
Operating Temperature Range(�C)
-40 to 85
Pin/Package
8MSOP, 8SOIC
SN65EPT22 特性
Dual 3.3V LVTTL to LVPECL Buffer
Operating Range
LVPECL VCC = 3.0 V to 3.6 V With
GND = 0 V
Support for Clock Frequencies to 2.0 GHz (typ)
420 ps Typical Propagation Delay
Deterministic HIGH Output Value for Open Input Conditions
Built-in Temperature Compensation
Drop in Compatible to MC100ELT23
PNP Single Ended Inputs for Minimal Loading
APPLICATIONS
Data and Clock Transmission Over Backplane
Signaling Level Conversion
SN65EPT22 芯片订购指南
器件
状态
温度
价格
封装 | 引脚
封装数量 | 封装载体
丝印标记
SN65EPT22D
ACTIVE
-40 to 85
1.45 | 1ku
SOIC (D) | 8 75 | TUBE
SN65EPT22DR
ACTIVE
-40 to 85
1.20 | 1ku
SOIC (D) | 8 2500 | LARGE T&R
SN65EPT22 质量与无铅数据
器件
环保计划*
铅/焊球涂层
MSL 等级/回流焊峰
环保信息与无铅 (Pb-free)
DPPM / MTBF / FIT 率
SN65EPT22D
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65EPT22D
SN65EPT22D
SN65EPT22DR
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65EPT22DR
SN65EPT22DR
SN65EPT22 应用技术支持与电子电路设计开发资源下载
SN65EPT22 数据资料 dataSheet 下载 .PDF TI 德州仪器PECL PHY选型与价格 . xls 所选封装材料的热学和电学性质 (PDF 645 KB)使用数字隔离器设计隔离式 I2C 总线接口 (zhct119.PDF, 339 KB)1Q 2011 Issue Analog Applications Journal (slyt399.PDF, 964 KB)接口选择指南 (Rev. D) (PDF 2994 KB)Signaling Rate vs. Distance for Differential Buffers (PDF 420 KB)Q1 2009 Issue Analog Applications Journal (slyt319.PDF, 1.39 MB)Isolated RS-485 Reference Design (PDF 80 KB)无铅组件涂层的保存期评估 (PDF 1305 KB)Analog Signal Chain Guide (8.62 MB)Industrial Interface IC Solutions (101 KB)
SN65EPT22 工具和软件
The SN65EPT22 is a low power dual LVTTL to LVPECL translator device. The device includes circuitry to maintain known logic HIGH level when inputs are in open condition. The SN65EPT22 is housed in an industry standard SOIC-8 package and is also available in TSSOP-8 package option.
