SN65EPT23 3.3V ECL 差动接收器
SN65EPT23
Signaling Rate(Mbps)
600
Input Signal
LVPECL,LVDS
Output Signal
LVTTL,CMOS
No. of Rx
2
No. of Tx
2
Supply Voltage(s)(V)
3.3
ICC(Max)(mA)
25
Rx tpd(Typ)(ns)
1.3
Operating Temperature Range(�C)
-40 to 85
Pin/Package
8MSOP, 8SOIC
SN65EPT23 特性
Dual 3.3 V Differential LVPECL/LVDS to
LVTTL/LVCMOS Buffer Translator
24 mA LVTTL Ouputs
Operating Range
VCC = 3.0 V to 3.6 V
GND = 0 V
Support for Clock Frequencies > 300 MHz
2.0 ns Typical Propagation Delay
Built-in Temperature Compensation
Drop in Compatible to MC100EPT23
APPLICATIONS
Data and Clock Transmission Over Backplane
Signaling Level Conversion for Clock or Data
SN65EPT23 芯片订购指南
器件
状态
温度
价格
封装 | 引脚
封装数量 | 封装载体
丝印标记
SN65EPT23D
ACTIVE
-40 to 85
1.45 | 1ku
SOIC (D) | 8 75 | TUBE
SN65EPT23DR
ACTIVE
-40 to 85
1.20 | 1ku
SOIC (D) | 8 2500 | LARGE T&R
SN65EPT23 质量与无铅数据
器件
环保计划*
铅/焊球涂层
MSL 等级/回流焊峰
环保信息与无铅 (Pb-free)
DPPM / MTBF / FIT 率
SN65EPT23D
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65EPT23D
SN65EPT23D
SN65EPT23DR
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65EPT23DR
SN65EPT23DR
SN65EPT23 应用技术支持与电子电路设计开发资源下载
SN65EPT23 数据资料 dataSheet 下载 .PDF TI 德州仪器PECL PHY选型与价格 . xls 所选封装材料的热学和电学性质 (PDF 645 KB)使用数字隔离器设计隔离式 I2C 总线接口 (zhct119.PDF, 339 KB)1Q 2011 Issue Analog Applications Journal (slyt399.PDF, 964 KB)接口选择指南 (Rev. D) (PDF 2994 KB)Signaling Rate vs. Distance for Differential Buffers (PDF 420 KB)Q1 2009 Issue Analog Applications Journal (slyt319.PDF, 1.39 MB)Isolated RS-485 Reference Design (PDF 80 KB)无铅组件涂层的保存期评估 (PDF 1305 KB)Analog Signal Chain Guide (8.62 MB)Industrial Interface IC Solutions (101 KB)
SN65EPT23 工具和软件
The SN65EPT23 is a low power dual LVPECL/LVDS to LVTTL/LVCMOS translator device. The device includes circuitry to maintain inputs at Vcc/2 when left open. The SN65EPT23 is housed in an industry standard SOIC-8 package and is also available in TSSOP-8 option.
