SN65LV1224B-EP
The SN65LV1023A serializer and SN65LV1224B deserializer comprise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz to 66 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 792-Mbps payload encoded throughput.
Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC patterns or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer establishes lock within specified, shorter time parameters.
The device can be entered into a power-down state when no data transfer is required.
|
SN65LV1224B-EP |
| Data Throughput(MB/s) |
660 |
| Number of Parallel Outputs |
10 |
| Serial Data Receiver Channels |
2 |
| PLL Frequency(MHz) |
10 - 66 |
| ICC(mA) |
80 |
| Supply Voltage(s)(V) |
3.3 |
| Pin/Package |
28SSOP |
| Operating Temperature Range(C) |
-55 to 125 |
| Receiver tpd(ns) |
8 |
| Receiver (Vth)(mV) |
50 |
| Type of Line Circuit |
LVDS |
SN65LV1224B-EP 特性
- Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
- Extended Temperature Performance of -55°C to 125°C
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product-Change Notification
- Qualification Pedigree(1)
- 100-Mbps to 660-Mbps Serial LVDS DataPayload Bandwidth at 10-MHz to 66-MHz System Clock
- Pin-Compatible Superset of DS92LV1023/DS92LV1224
- Chipset (Serializer/Deserializer) Power Consumption <450 mW (Typ) at 66 MHz
- Synchronization Mode for Faster Lock
- Lock Indicator
- No External Components Required for PLL
- 28-Pin SSOP and Space Saving 5 × 5 mm QFN Packages Available
- Programmable Edge Trigger on Clock
- Flow-Through Pinout for Easy PCB Layout
SN65LV1224B-EP 芯片订购指南
| 器件 |
状态 |
温度 |
价格 |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| SN65LV1224BMDBREP |
ACTIVE |
-55 to 125 |
9.80 | 100u |
SSOP (DB) | 28 |
2000 | LARGE T&R |
|
| V62/06677-02XE |
ACTIVE |
-55 to 125 |
9.80 | 100u |
SSOP (DB) | 28 |
2000 | LARGE T&R |
|
SN65LV1224B-EP 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| SN65LV1224BMDBREP |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN65LV1224BMDBREP |
SN65LV1224BMDBREP |
| V62/06677-02XE |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
V62/06677-02XE |
V62/06677-02XE |
SN65LV1224B-EP 应用技术支持与电子电路设计开发资源下载
- SN65LV1224B-EP 数据资料 dataSheet 下载.PDF
- TI 德州仪器串行器和解串器选型与价格 . xls
- 所选封装材料的热学和电学性质 (PDF 645 KB)
- 使用数字隔离器设计隔离式 I2C 总线接口 (zhct119.PDF, 339 KB)
- 高性能SERDES及其在CPRI 接口的应用分析 (zhca076.HTM, 8 KB)
- 1Q 2011 Issue Analog Applications Journal (slyt399.PDF, 964 KB)
- 接口选择指南 (Rev. D) (PDF 2994 KB)
- Signaling Rate vs. Distance for Differential Buffers (PDF 420 KB)
- Q1 2009 Issue Analog Applications Journal (slyt319.PDF, 1.39 MB)
- Isolated RS-485 Reference Design (PDF 80 KB)
- 无铅组件涂层的保存期评估 (PDF 1305 KB)
- Analog Signal Chain Guide (8.62 MB)
- Industrial Interface IC Solutions (101 KB)
SN65LV1224B-EP 工具和软件
