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SN65LVDM320 具有直通式引脚的四路 LVDS 发送器

The SN65LVDM320 is an 8-bit data storage register with differential line drivers and receivers that are electrically compatible with ANSI EIA/TIA-644 for multipoint architectures with standard-compliant parallel transfer rates of 475 Mbps. The SN65LVDM320 includes transmitter and receiver data registers that remain active regardless of the state of their associated outputs.

The logic element for data flow in each direction is configured by mode-control inputs. IMODE1 and IMODE2 control data flow in the B-to-A (bus side to digital side) direction when configured as a buffer, a D-type flip-flop, or a D-type latch. OMODE1 and OMODE2 control data flow in each of the operating modes for the A-to-B (digital side to bus side) direction

	SN65LVDM320
No. of Rx	8
No. of Tx	8
Input Signal	LVCMOS
Output Signal	LVDM
Signaling Rate(Mbps)	475
Supply Voltage(s)(V)	3.3
ICC(Max)(mA)	130
Part-to-Part Skew(Max)(ps)	600
Rx tpd(Typ)(ns)	3.3
Tx tpd(Typ)(ns)	3.3
Pin/Package	64TSSOP
Operating Temperature Range(�C)	-40 to 85
ESD HBM(kV)	12

SN65LVDM320 特性

• 8-Bit Bidirectional Data Storage Register With Full Parallel Access
• Parallel Transfer Rates
  • Buffer Mode: Up to 475 Megatransfers
  • Flip-Flop Mode: Up to 300 Megatransfers
  • Latch Mode: Up to 300 Megatransfers
• Operates With a Single 3.3-V Supply
• Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV Across a 50- Load
• Bus and Logic Loopback Capability
• Very Low Radiation Emission
• Low Skew Performance
  • Pulse Skew Less Than 100 ps
  • Output Skew Less Than 320 ps
  • Part-to-Part Skew Less Than 1 ns
• Open-Circuit Differential Receiver Fail Safe Assures a Low-Level Output
• Reset at Power Up
• 12-kV Bus-Pin ESD Protection
• Bus Pins Remain High-Impedance When Disabled or With VCC Below 1.5 V for Power-Up/Down Glitch-Free Performance and Hot Plugging
• 5-V Tolerant LVCMOS Inputs
• APPLICATIONS
  • Telecom Switching

SN65LVDM320 芯片订购指南

器件	状态	温度	价格	封装 | 引脚	封装数量 | 封装载体	丝印标记
SN65LVDM320DGG	ACTIVE	-40 to 85	10.05 | 1ku	TSSOP (DGG) | 64	25 | TUBE
SN65LVDM320DGGG4	ACTIVE	-40 to 85	10.05 | 1ku	TSSOP (DGG) | 64	25 | TUBE

SN65LVDM320 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN65LVDM320DGG	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-2-260C-1 YEAR	SN65LVDM320DGG	SN65LVDM320DGG
SN65LVDM320DGGG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-2-260C-1 YEAR	SN65LVDM320DGGG4	SN65LVDM320DGGG4

SN65LVDM320 应用技术支持与电子电路设计开发资源下载

1. SN65LVDM320 数据资料 dataSheet 下载.PDF
2. TI 德州仪器M-LVDS PHYs选型与价格 . xls
3. 所选封装材料的热学和电学性质 (PDF 645 KB)
4. 使用数字隔离器设计隔离式 I2C 总线接口 (zhct119.PDF, 339 KB)
5. 1Q 2011 Issue Analog Applications Journal (slyt399.PDF, 964 KB)
6. 接口选择指南 (Rev. D) (PDF 2994 KB)
7. Signaling Rate vs. Distance for Differential Buffers (PDF 420 KB)
8. Q1 2009 Issue Analog Applications Journal (slyt319.PDF, 1.39 MB)
9. Isolated RS-485 Reference Design (PDF 80 KB)
10. 无铅组件涂层的保存期评估 (PDF 1305 KB)
11. Analog Signal Chain Guide (8.62 MB)
12. Industrial Interface IC Solutions (101 KB)