SN65LVDS108 1:8 LVDS 时钟扇出缓冲器
The SN65LVDS108 is configured as one differential line receiver connected to eight differential line drivers. Individual output enables are provided for each output and an additional enable is provided for all outputs.
The line receivers and line drivers implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS, as specified in EIA/TIA-644, is a data signaling technique that offers low power, low noise emission, high noise immunity, and high switching speeds. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)
The intended application of this device, and the LVDS signaling technique, is for point-to-point or point-to-multipoint (distributed simplex) baseband data transmission on controlled impedance media of approximately 100
| SN65LVDS104 | SN65LVDS105 | SN65LVDS108 | SN65LVDS116 | |
| Input Signal | 315 | 315 | 311 | 311 |
| Output Signal | 3.3 | 3.3 | 3.3 | 3.3 |
| No. of Rx | LVDS | LVTTL | LVDS | LVDS |
| No. of Tx | 4 | 4 | 8 | 16 |
| Operating Temperature Range(°C) | LVDS | LVDS | LVDS | LVDS |
| ESD HBM(kV) | 16SOIC, 16TSSOP | 16SOIC, 16TSSOP | 38TSSOP | 64TSSOP |
| Approx. Price (US$) | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 |
SN65LVDS108 特性
- One Line Receiver and Eight Line Drivers Configured as an 8-Port LVDS Repeater
- Line Receiver and Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
- Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz
- Enabling Logic Allows Individual Control of Each Driver Output, Plus All Outputs
- Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and a 100-
Load
- Electrically Compatible With LVDS, PECL, LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT, SSTL, or HSTL Outputs With External Termination Networks
- Propagation Delay Times < 4.7 ns
- Output Skew Less Than 300 ps andPart-to-Part Skew Less Than 1.5 ns
- Total Power Dissipation at 200 MHz Typically Less Than 330 mW With 8 Channels Enabled
- Driver Outputs or Receiver Input Equals High Impedance When Disabled or With VCC < 1.5 V
- Bus-Pin ESD Protection Exceeds 12 kV
- Packaged in Thin Shrink Small-Outline Package With 20-Mil Terminal Pitch
SN65LVDS108 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN65LVDS108DBT | ACTIVE | -40 to 85 | 3.85 | 1ku | TSSOP (DBT) | 38 | 50 | TUBE | |
| SN65LVDS108DBTG4 | ACTIVE | -40 to 85 | 3.85 | 1ku | TSSOP (DBT) | 38 | 50 | TUBE | |
| SN65LVDS108DBTR | ACTIVE | -40 to 85 | 3.20 | 1ku | TSSOP (DBT) | 38 | 2000 | LARGE T&R | |
| SN65LVDS108DBTRG4 | ACTIVE | -40 to 85 | 3.20 | 1ku | TSSOP (DBT) | 38 | 2000 | LARGE T&R |
SN65LVDS108 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN65LVDS108DBT | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-2-260C-1 YEAR | SN65LVDS108DBT | SN65LVDS108DBT |
| SN65LVDS108DBTG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-2-260C-1 YEAR | SN65LVDS108DBTG4 | SN65LVDS108DBTG4 |
| SN65LVDS108DBTR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-2-260C-1 YEAR | SN65LVDS108DBTR | SN65LVDS108DBTR |
| SN65LVDS108DBTRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-2-260C-1 YEAR | SN65LVDS108DBTRG4 | SN65LVDS108DBTRG4 |
SN65LVDS108 应用技术支持与电子电路设计开发资源下载
- SN65LVDS108 数据资料 dataSheet 下载.PDF
- TI 德州仪器LVDS PHYs选型与价格 . xls
- 所选封装材料的热学和电学性质 (PDF 645 KB)
- 使用数字隔离器设计隔离式 I2C 总线接口 (zhct119.PDF, 339 KB)
- 1Q 2011 Issue Analog Applications Journal (slyt399.PDF, 964 KB)
- 接口选择指南 (Rev. D) (PDF 2994 KB)
- Signaling Rate vs. Distance for Differential Buffers (PDF 420 KB)
- Q1 2009 Issue Analog Applications Journal (slyt319.PDF, 1.39 MB)
- Isolated RS-485 Reference Design (PDF 80 KB)
- 无铅组件涂层的保存期评估 (PDF 1305 KB)
- Analog Signal Chain Guide (8.62 MB)
- Industrial Interface IC Solutions (101 KB)
