SN65LVDS387 16 通道 LVDS 接收器
This family of four, eight, and sixteen differential line drivers implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the sixteen current-mode drivers will deliver a minimum differential output voltage magnitude of 247 mV into a 100-
The intended application of this device and signaling technique is for point-to-point and multidrop baseband data transmission over controlled impedance media of approximately 100
SN65LVDS386 SN65LVDS387 SN65LVDS388A SN65LVDS389 SN65LVDT386 SN65LVDT388A SN75LVDS388A SN75LVDT388A
Input Signal
LVDS
LVTTL
LVDS
LVTTL
LVDS
LVDS
LVDS
LVDS
Output Signal
LVTTL
LVDS
LVTTL
LVDS
LVTTL
LVTTL
LVTTL
LVTTL
No. of Rx
16
8
16
8
8
8
No. of Tx
16
8
Signaling Rate(Mbps)
630
630
630
630
630
630
630
630
Supply Voltage(s)(V)
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
ICC(Max)(mA)
70
95
40
70
70
40
40
40
Rx tpd(Typ)(ns)
2.5
2.6
2.6
2.6
2.6
2.6
Tx tpd(Typ)(ns)
1.7
1.7
Part-to-Part Skew(Max)(ps)
1000
1500
1000
1500
1000
1000
1000
1000
Pin/Package
64TSSOP
64TSSOP
38TSSOP
38TSSOP
64TSSOP
38TSSOP
38TSSOP
38TSSOP
Operating Temperature Range(°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
0 to 70
ESD HBM(kV)
15
15
15
15
15
15
4
4
Approx. Price (US$)
4.60 | 1ku
4.60 | 1ku
2.00 | 1ku
2.00 | 1ku
4.85 | 1ku
2.10 | 1ku
2.40 | 1ku
2.10 | 1ku
SN65LVDS387 特性
Four ('391), Eight ('389) or Sixteen ('387) Line Drivers Meet or Exceed the Requirements of ANSI EIA/ TIA-644 Standard
Designed for Signaling Rates Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and a 100- Propagation Delay Times Less Than 2.9 ns
Output Skew Is Less Than 150 ps
Part-to-Part Skew Is Less Than 1.5 ns
35-mW Total Power Dissipation in Each Driver Operating at 200 MHz
Driver Is High Impedance When Disabled or With VCC < 1.5 V
SN65' Version Bus-Pin ESD Protection Exceeds 15 kV
Packaged in Thin Shrink Small-Outline Package With 20-mil Terminal Pitch
Low-Voltage TTL (LVTTL) Logic Inputs Are 5-V Tolerant
SN65LVDS387 芯片订购指南
器件
状态
温度
价格
封装 | 引脚
封装数量 | 封装载体
丝印标记
SN65LVDS387DGG
ACTIVE
-40 to 85
5.40 | 1ku
TSSOP (DGG) | 64 25 | TUBE
SN65LVDS387DGGG4
ACTIVE
-40 to 85
5.40 | 1ku
TSSOP (DGG) | 64 25 | TUBE
SN65LVDS387DGGR
ACTIVE
-40 to 85
4.60 | 1ku
TSSOP (DGG) | 64 2000 | LARGE T&R
SN65LVDS387DGGRG4
ACTIVE
-40 to 85
4.60 | 1ku
TSSOP (DGG) | 64 2000 | LARGE T&R
SN65LVDS387 质量与无铅数据
器件
环保计划*
铅/焊球涂层
MSL 等级/回流焊峰
环保信息与无铅 (Pb-free)
DPPM / MTBF / FIT 率
SN65LVDS387DGG
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SN65LVDS387DGG
SN65LVDS387DGG
SN65LVDS387DGGG4
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SN65LVDS387DGGG4 SN65LVDS387DGGG4
SN65LVDS387DGGR
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SN65LVDS387DGGR
SN65LVDS387DGGR
SN65LVDS387DGGRG4
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SN65LVDS387DGGRG4 SN65LVDS387DGGRG4
SN65LVDS387 应用技术支持与电子电路设计开发资源下载
SN65LVDS387 数据资料 dataSheet 下载 .PDF TI 德州仪器LVDS PHYs选型与价格 . xls 所选封装材料的热学和电学性质 (PDF 645 KB)使用数字隔离器设计隔离式 I2C 总线接口 (zhct119.PDF, 339 KB)1Q 2011 Issue Analog Applications Journal (slyt399.PDF, 964 KB)接口选择指南 (Rev. D) (PDF 2994 KB)Signaling Rate vs. Distance for Differential Buffers (PDF 420 KB)Q1 2009 Issue Analog Applications Journal (slyt319.PDF, 1.39 MB)Isolated RS-485 Reference Design (PDF 80 KB)无铅组件涂层的保存期评估 (PDF 1305 KB)Analog Signal Chain Guide (8.62 MB)Industrial Interface IC Solutions (101 KB)
load when enabled. 
up to 630 Mbps With Very Low Radiation (EMI)
