SN65LVDS94 Serdes（串行器/解串器）接收器
The SN65LVDS94 LVDS serdes (serializer/deserializer) receiver contains four serial-in 7-bit parallel-out shift registers, a 7× clock synthesizer, and five low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the SN65LVDS93 and SN65LVDS95, over five balanced-pair conductors and expansion to 28 bits of single-ended LVTTL synchronous data at a lower transfer rate.
When receiving, the high-speed LVDS data is received and loaded into registers at the rate seven times the LVDS input clock (CLKIN). The data is then unloaded to a 28-bit wide LVTTL parallel bus at the CLKIN rate. A phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the expanded data
|
SN65LVDS94 |
| Data Throughput(MB/s) |
227.5 |
| Number of Parallel Outputs |
28 |
| Serial Data Receiver Channels |
4 |
| PLL Frequency(MHz) |
20 - 65 |
| ICC(mA) |
74 |
| Supply Voltage(s)(V) |
3.3 |
| Pin/Package |
56TSSOP |
| Footprint |
SN65LVDS84 |
| Operating Temperature Range(C) |
-40 to 85 |
| Receiver tpd(ns) |
8.7 |
| Receiver (Vth)(mV) |
+/-100 |
| Type of Line Circuit |
LVDS |
SN65LVDS94 特性
- 4:28 Data Channel Expansion at up to 1.904 Gigabits per Second Throughput
- Suited for Point-to-Point Subsystem Communication With Very Low EMI
- 4 Data Channels and Clock Low-Voltage Differential Channels in and 28 Data and Clock Out Low-Voltage TTL Channels Out
- Operates From a Single 3.3-V Supply and 250 mW (Typ)
- 5-V Tolerant SHTDN\ Input
- Rising Clock Edge Triggered Outputs
- Bus Pins Tolerate 4-kV HBM ESD
- Packaged in Thin Shrink Small-Outline Package With 20 Mil Terminal Pitch
- Consumes <1 mW When Disabled
- Wide Phase-Lock Input Frequency Range
- No External Components Required for PLL
- Meets or Exceeds the Requirements of ANSI EIA/TIA-644 Standard
- Industrial Temperature Qualified TA = -40°C to 85°C
- Replacement for the DS90CR286
SN65LVDS94 芯片订购指南
SN65LVDS94 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| SN65LVDS94DGG |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-2-260C-1 YEAR |
SN65LVDS94DGG |
SN65LVDS94DGG |
| SN65LVDS94DGGG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-2-260C-1 YEAR |
SN65LVDS94DGGG4 |
SN65LVDS94DGGG4 |
| SN65LVDS94DGGR |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-2-260C-1 YEAR |
SN65LVDS94DGGR |
SN65LVDS94DGGR |
| SN65LVDS94DGGRG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-2-260C-1 YEAR |
SN65LVDS94DGGRG4 |
SN65LVDS94DGGRG4 |
SN65LVDS94 应用技术支持与电子电路设计开发资源下载
- SN65LVDS94 数据资料 dataSheet 下载.PDF
- TI 德州仪器串行器和解串器选型与价格 . xls
- 所选封装材料的热学和电学性质 (PDF 645 KB)
- 使用数字隔离器设计隔离式 I2C 总线接口 (zhct119.PDF, 339 KB)
- 高性能SERDES及其在CPRI 接口的应用分析 (zhca076.HTM, 8 KB)
- 1Q 2011 Issue Analog Applications Journal (slyt399.PDF, 964 KB)
- 接口选择指南 (Rev. D) (PDF 2994 KB)
- Signaling Rate vs. Distance for Differential Buffers (PDF 420 KB)
- Q1 2009 Issue Analog Applications Journal (slyt319.PDF, 1.39 MB)
- Isolated RS-485 Reference Design (PDF 80 KB)
- 无铅组件涂层的保存期评估 (PDF 1305 KB)
- Analog Signal Chain Guide (8.62 MB)
- Industrial Interface IC Solutions (101 KB)
SN65LVDS94 工具和软件
