SN65LVDS96 Serdes（串行器/解串器）接收器
The SN65LVDS96 LVDS serdes (serializer/deserializer) receiver contains three serial-in 7-bit parallel-out shift registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such asthe SN65LVDS95, over four balanced-pair conductors and expansion to 21 bits of single-ended LVTTL synchronous data at a lower transfer rate.
When receiving, the high-speed LVDS data is received and loaded into registers at the rate of seven times the LVDS input clock (CLKIN). The data is then unloaded to a 21-bit wide LVTTL parallel bus at the CLKIN rate. A phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the expanded data
|
SN65LVDS96 |
| Data Throughput(MB/s) |
170.625 |
| Number of Parallel Outputs |
21 |
| Serial Data Receiver Channels |
3 |
| PLL Frequency(MHz) |
20 - 68 |
| ICC(mA) |
94 |
| Supply Voltage(s)(V) |
3.3 |
| Pin/Package |
48TSSOP |
| Footprint |
SN65LVDS86 |
| Operating Temperature Range(C) |
-40 to 85 |
| Receiver tpd(ns) |
8.7 |
| Receiver (Vth)(mV) |
+/-100 |
| Type of Line Circuit |
LVDS |
SN65LVDS96 特性
- 3:21 Data Channel Compression at up to1.428 Gigabits/s Throughput
- Suited for Point-to-Point Subsystem Communication With Very Low EMI
- 3 Data Channels and Clock Low-Voltage Differential Channels in and 21 Data and Clock Low-Voltage TTL Channels Out
- Operates From a Single 3.3-V Supply and 250 mW (Typ)
- 5-V Tolerant SHTDN Input
- Rising Clock Edge Triggered Outputs
- Bus Pins Tolerate 4-kV HBM ESD
- Packaged in Thin Shrink Small-Outline Package With 20 Mil Terminal Pitch
- Consumes <1 mW When Disabled
- Wide Phase-Lock Input Frequency Range 20 MHz to 68 MHz
- No External Components Required for PLL
- Inputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
- Industrial Temperature Qualified TA = -40°C to 85°C
- Replacement for the DS90CR216
SN65LVDS96 芯片订购指南
| 器件 |
状态 |
温度 |
价格 |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| SN65LVDS96DGG |
ACTIVE |
-40 to 85 |
4.70 | 1ku |
TSSOP (DGG) | 48 |
40 | TUBE |
|
| SN65LVDS96DGGG4 |
ACTIVE |
-40 to 85 |
4.70 | 1ku |
TSSOP (DGG) | 48 |
40 | TUBE |
|
| SN65LVDS96DGGR |
ACTIVE |
-40 to 85 |
3.95 | 1ku |
TSSOP (DGG) | 48 |
2000 | LARGE T&R |
|
| SN65LVDS96DGGRG4 |
ACTIVE |
-40 to 85 |
3.95 | 1ku |
TSSOP (DGG) | 48 |
2000 | LARGE T&R |
|
SN65LVDS96 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| SN65LVDS96DGG |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-2-260C-1 YEAR |
SN65LVDS96DGG |
SN65LVDS96DGG |
| SN65LVDS96DGGG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-2-260C-1 YEAR |
SN65LVDS96DGGG4 |
SN65LVDS96DGGG4 |
| SN65LVDS96DGGR |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-2-260C-1 YEAR |
SN65LVDS96DGGR |
SN65LVDS96DGGR |
| SN65LVDS96DGGRG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-2-260C-1 YEAR |
SN65LVDS96DGGRG4 |
SN65LVDS96DGGRG4 |
SN65LVDS96 应用技术支持与电子电路设计开发资源下载
- SN65LVDS96 数据资料 dataSheet 下载.PDF
- TI 德州仪器串行器和解串器选型与价格 . xls
- 所选封装材料的热学和电学性质 (PDF 645 KB)
- 使用数字隔离器设计隔离式 I2C 总线接口 (zhct119.PDF, 339 KB)
- 高性能SERDES及其在CPRI 接口的应用分析 (zhca076.HTM, 8 KB)
- 1Q 2011 Issue Analog Applications Journal (slyt399.PDF, 964 KB)
- 接口选择指南 (Rev. D) (PDF 2994 KB)
- Signaling Rate vs. Distance for Differential Buffers (PDF 420 KB)
- Q1 2009 Issue Analog Applications Journal (slyt319.PDF, 1.39 MB)
- Isolated RS-485 Reference Design (PDF 80 KB)
- 无铅组件涂层的保存期评估 (PDF 1305 KB)
- Analog Signal Chain Guide (8.62 MB)
- Industrial Interface IC Solutions (101 KB)
SN65LVDS96 工具和软件
