SN65MLVD082 8 通道半双工 M-LVDS 收发器

The SN65MLVD080 and SN65MLVD082 provide eight half-duplex transceivers for transmitting and receiving Multipoint-Low-Voltage Differential Signals in full compliance with the TIA/EIA-899 (M-LVDS) standard, which are optimized to operate at signaling rates up to 250 Mbps. The driver outputs have been designed to support multipoint buses presenting loads as low as 30- and incorporates controlled transition times to allow for stubs off of the backbone transmission line.

The M-LVDS standard defines two types of receivers, designated as Type-1 and Type-2. Type-1 receivers (SN65MLVD080) have thresholds centered about zero with 25 mV of hysteresis to prevent output oscillations with loss of input; Type-2 receivers (SN65MLVD082) implement a failsafe by using an offset threshold

	SN65LVDM1676	SN65LVDM1677	SN65MLVD080	SN65MLVD082
No. of Rx	16	16	8	8
No. of Tx	16	16	8	8
Input Signal	LVDM, LVTTL	LVDM, LVTTL	LVTTL, M-LVDS	LVTTL, M-LVDS
Output Signal	LVDM, LVTTL	LVDM, LVTTL	M-LVDS, TTL	M-LVDS, TTL
Signaling Rate(Mbps)	650TX/250RX	650TX/250RX	250	250
Supply Voltage(s)(V)	3.3	3.3	3.3	3.3
ICC(Max)(mA)	175	175	180	180
Receiver Type			1	2
Part-to-Part Skew(Max)(ps)	1000	1000	600	600
Rx tpd(Typ)(ns)	3	3	6	6
Tx tpd(Typ)(ns)	2.5	2.5	2.4	2.4
Pin/Package	64TSSOP	64TSSOP	64TSSOP	64TSSOP
Operating Temperature Range(�C)	-40 to 85	-40 to 85	-40 to 85	-40 to 85
ESD HBM(kV)	15	15	8	8

SN65MLVD082 特性

Low-Voltage Differential 30- Line Drivers and Receivers for Signaling Rates(1) Up to 250 Mbps; Clock Frequencies Up to 125 MHz
Meets or Exceeds the M-LVDS Standard TIA/EIA-899 for Multipoint Data Interchange
Controlled Driver Output Voltage Transition Times for Improved Signal Quality
–1 V to 3.4 V Common-Mode Voltage Range Allows Data Transfer With 2 V of Ground Noise
Bus Pins High Impedance When Driver Disabled or VCC ≤ 1.5 V
Independent Enables for each Driver
Bus Pin ESD Protection Exceeds 8 kV
Packaged in 64-Pin TSSOP (DGG)
M-LVDS Bus Power Up/Down Glitch Free
APPLICATIONS
- Parallel Multipoint Data and Clock Transmission Via Backplanes and Cables
- Low-Power High-Speed Short-Reach Alternative to TIA/EIA-485
- Cellular Base Stations
- Central-Office Switches
- Network Switches and Routers

SN65MLVD082 芯片订购指南

器件	状态	温度	价格	封装 \| 引脚	封装数量 \| 封装载体	丝印标记
SN65MLVD082DGG	ACTIVE	-40 to 85	3.60 \| 1ku	TSSOP (DGG) \| 64	25 \| TUBE
SN65MLVD082DGGG4	ACTIVE	-40 to 85	3.60 \| 1ku	TSSOP (DGG) \| 64	25 \| TUBE
SN65MLVD082DGGR	ACTIVE	-40 to 85	3.00 \| 1ku	TSSOP (DGG) \| 64	2000 \| LARGE T&R
SN65MLVD082DGGRG4	ACTIVE	-40 to 85	3.00 \| 1ku	TSSOP (DGG) \| 64	2000 \| LARGE T&R

SN65MLVD082 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN65MLVD082DGG	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-2-260C-1 YEAR	SN65MLVD082DGG	SN65MLVD082DGG
SN65MLVD082DGGG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-2-260C-1 YEAR	SN65MLVD082DGGG4	SN65MLVD082DGGG4
SN65MLVD082DGGR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-2-260C-1 YEAR	SN65MLVD082DGGR	SN65MLVD082DGGR
SN65MLVD082DGGRG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-2-260C-1 YEAR	SN65MLVD082DGGRG4	SN65MLVD082DGGRG4

SN65MLVD082 应用技术支持与电子电路设计开发资源下载

SN65MLVD082 数据资料 dataSheet 下载.PDF
TI 德州仪器M-LVDS PHYs选型与价格 . xls
所选封装材料的热学和电学性质 (PDF 645 KB)
使用数字隔离器设计隔离式 I2C 总线接口 (zhct119.PDF, 339 KB)
1Q 2011 Issue Analog Applications Journal (slyt399.PDF, 964 KB)
接口选择指南 (Rev. D) (PDF 2994 KB)
Signaling Rate vs. Distance for Differential Buffers (PDF 420 KB)
Q1 2009 Issue Analog Applications Journal (slyt319.PDF, 1.39 MB)
Isolated RS-485 Reference Design (PDF 80 KB)
无铅组件涂层的保存期评估 (PDF 1305 KB)
Analog Signal Chain Guide (8.62 MB)
Industrial Interface IC Solutions (101 KB)