SN75LVDT1422 全双工串行器/解串器
The SN75LVDT1422 Full Duplex Serializer/Deserializer incorporates a 14-bit serializer and a 14-bit deserializer. Operation of the serializer is independent of the operation of the deserializer. The 14-bit serializer accepts 14 TTL input lines and generates 2 LVDS high-speed serial streams plus one LVDS clock signal. The 14-bit deserializer accepts 3 LVDS input signals (2 high-speed serial streams and one LVDS clock signal) and drives out 14 TTL data signals plus one TTL clock.
The serializer loads 14 data bits into registers upon the rising or falling edge of the input clock signal (CLK IN). Rising or falling edge operation can be selected via the R/F select pin for the transmitter only. The frequency of CLK IN is multiplied seven times and then used to unload the data registers in 7-bit slices
|
SN75LVDT1422 |
| Data Throughput(MB/s) |
175 |
| Number of Parallel Inputs |
15 |
| Number of Parallel Outputs |
15 |
| Serial Data Receiver Channels |
2 |
| Serial Data Transmitter Channels |
2 |
| PLL Frequency(MHz) |
10 - 100 |
| ICC(mA) |
49 |
| Supply Voltage(s)(V) |
3.3 |
| Pin/Package |
64TQFP |
| Footprint |
64 pin TQFP[JR] |
| Operating Temperature Range(C) |
-10 to 70 |
| Driver tpd(ns) |
3.95 |
| Receiver tpd(ns) |
9 |
| Receiver (Vth)(mV) |
100 |
| Type of Line Circuit |
SerDes |
SN75LVDT1422 特性
- 10 MHz to 100 MHz Shift Clock Support
- 175 Mbytes/sec In TX/RX Modes
- Reduces Cable Size, Cost, and System EMI
- Bidirectional Data Communication
- Total Power < 360 mW Typ at 100-MHz Worst Case Pattern
- Power-Down Mode: < 500 µW Typ
- No External Components Required for PLL
- Inputs and Outputs Compatible with TIA/EIA-644 LVDS Standard
- ESD Rating > 5 kV (HBM)
- Integrated Termination Resistor
- Supports Spread Spectrum Clocking
- 64-Pin TQFP Package (PAG)
- APPLICATIONS
- Flash Memory Cards
- Plain Paper Copiers
- Printers
SN75LVDT1422 芯片订购指南
| 器件 |
状态 |
温度 |
价格 |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| SN75LVDT1422PAG |
ACTIVE |
-10 to 70 |
5.60 | 1ku |
TQFP (PAG) | 64 |
160 | JEDEC TRAY (5+1) |
|
| SN75LVDT1422PAGG4 |
ACTIVE |
-10 to 70 |
5.60 | 1ku |
TQFP (PAG) | 64 |
160 | JEDEC TRAY (5+1) |
|
| SN75LVDT1422PAGR |
ACTIVE |
-10 to 70 |
4.65 | 1ku |
TQFP (PAG) | 64 |
1500 | LARGE T&R |
|
| SN75LVDT1422PAGRG4 |
ACTIVE |
-10 to 70 |
4.65 | 1ku |
TQFP (PAG) | 64 |
1500 | LARGE T&R |
|
SN75LVDT1422 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| SN75LVDT1422PAG |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-3-260C-168 HR |
SN75LVDT1422PAG |
SN75LVDT1422PAG |
| SN75LVDT1422PAGG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-3-260C-168 HR |
SN75LVDT1422PAGG4 |
SN75LVDT1422PAGG4 |
| SN75LVDT1422PAGR |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-3-260C-168 HR |
SN75LVDT1422PAGR |
SN75LVDT1422PAGR |
| SN75LVDT1422PAGRG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-3-260C-168 HR |
SN75LVDT1422PAGRG4 |
SN75LVDT1422PAGRG4 |
SN75LVDT1422 应用技术支持与电子电路设计开发资源下载
- SN75LVDT1422 数据资料 dataSheet 下载.PDF
- TI 德州仪器串行器和解串器选型与价格 . xls
- 所选封装材料的热学和电学性质 (PDF 645 KB)
- 使用数字隔离器设计隔离式 I2C 总线接口 (zhct119.PDF, 339 KB)
- 高性能SERDES及其在CPRI 接口的应用分析 (zhca076.HTM, 8 KB)
- 1Q 2011 Issue Analog Applications Journal (slyt399.PDF, 964 KB)
- 接口选择指南 (Rev. D) (PDF 2994 KB)
- Signaling Rate vs. Distance for Differential Buffers (PDF 420 KB)
- Q1 2009 Issue Analog Applications Journal (slyt319.PDF, 1.39 MB)
- Isolated RS-485 Reference Design (PDF 80 KB)
- 无铅组件涂层的保存期评估 (PDF 1305 KB)
- Analog Signal Chain Guide (8.62 MB)
- Industrial Interface IC Solutions (101 KB)
SN75LVDT1422 工具和软件
