TL16C550C 具有 16 字节 FIFO 及自动流控制的单路 UART
The TL16C550C and the TL16C550CI are functional upgrades of the TL16C550B asynchronous communications element (ACE), which in turn is a functional upgrade of the TL16C450. Functionally equivalent to the TL16C450 on power up (character or TL16C450 mode), the TL16C550C and the TL16C550CI, like the TL16C550B, can be placed in an alternate FIFO mode. This relieves the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiver FIFO. In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software overload and increase system efficiency by automatically controlling serial data flow using RTS\ output and CTS\ input signals.
|
TL16C550C |
| Number of Channels |
1 |
| FIFOs(bytes) |
16 |
| Operating Voltage(V) |
5 / 3.3 |
| Operating Temperature Range(C) |
-40 to 85,0 to 70 |
| Pin/Package |
44PLCC, 48LQFP, 48TQFP |
| Rating |
Catalog |
| Tx / Rx FIFO INT Trig |
No / 4 Levels |
| Auto RTS/CTS |
Yes |
| CPU Interface |
X86 |
| Baud Rate (max) at Vcc = 3.3V and with 16X Sampling(Mbps) |
0.931 |
| Baud Rate (max) at Vcc = 5.0V and with 16X Sampling(Mbps) |
1.0 |
TL16C550C 特性
- Programmable Auto-RTS\ and Auto-CTS\
- In Auto-CTS\ Mode, CTS\ Controls Transmitter
- In Auto-RTS\ Mode, RCV FIFO Contents and Threshold Control RTS\
- Serial and Modem Control Outputs Drive a RJ11 Cable Directly When Equipment Is on the Same Power Drop
- Capable of Running With All Existing TL16C450 Software
- After Reset, All Registers Are Identical to the TL16C450 Register Set
- Up to 16-MHz Clock Rate for up to 1-Mbaud Operation
- In the TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data
- Programmable Baud Rate Generator Allows Division of Any Input Reference Clock by 1 to (216 –1) and Generates an Internal 16× Clock
- Standard Asynchronous Communication Bits (Start, Stop, and Parity) Added to or Deleted From the Serial Data Stream
- 5-V and 3.3-V Operation
- Independent Receiver Clock Input
- Transmit, Receive, Line Status, and Data Set Interrupts Independently Controlled
- Fully Programmable Serial Interface Characteristics:
- 5-, 6-, 7-, or 8-Bit Characters
- Even-, Odd-, or No-Parity Bit Generation and Detection
- 1-, 1 1/2-, or 2-Stop Bit Generation
- Baud Generation (dc to 1 Mbit/s)
- False-Start Bit Detection
- Complete Status Reporting Capabilities
TL16C550C 芯片订购指南
TL16C550C 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| TL16C550CFN |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-3-260C-168 HR |
TL16C550CFN |
TL16C550CFN |
| TL16C550CFNG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-3-260C-168 HR |
TL16C550CFNG4 |
TL16C550CFNG4 |
| TL16C550CFNR |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-3-260C-168 HR |
TL16C550CFNR |
TL16C550CFNR |
| TL16C550CFNRG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-3-260C-168 HR |
TL16C550CFNRG4 |
TL16C550CFNRG4 |
TL16C550C 应用技术支持与电子电路设计开发资源下载
- TL16C550C 数据资料 dataSheet 下载.PDF
- TI 德州仪器UART选型与价格 . xls
- 所选封装材料的热学和电学性质 (PDF 645 KB)
- 使用数字隔离器设计隔离式 I2C 总线接口 (zhct119.PDF, 339 KB)
- 高性能SERDES及其在CPRI 接口的应用分析 (zhca076.HTM, 8 KB)
- 1Q 2011 Issue Analog Applications Journal (slyt399.PDF, 964 KB)
- 接口选择指南 (Rev. D) (PDF 2994 KB)
- Signaling Rate vs. Distance for Differential Buffers (PDF 420 KB)
- Q1 2009 Issue Analog Applications Journal (slyt319.PDF, 1.39 MB)
- Isolated RS-485 Reference Design (PDF 80 KB)
- 无铅组件涂层的保存期评估 (PDF 1305 KB)
- Analog Signal Chain Guide (8.62 MB)
- Industrial Interface IC Solutions (101 KB)
TL16C550C 工具和软件
