TMS320C6205-200 定点数字信号处理器
The TMS320C62x™ DSPs (including the TMS320C6205 device) compose the fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C6205 (C6205) device is based on the high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making the C6205 an excellent choice for multichannel and multifunction applications.
With performance of up to 1600 million instructions per second (MIPS) at a clock rate of 200 MHz, the C6205 offers cost-effective solutions to high-performance DSP-programming challenges. The C6205 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units
|
TMS320C6205-200 |
| CPU |
1 C62x |
| Peak MMACS |
400 |
| Frequency (MHz) |
200 |
| RAM (KB) |
128 KB |
| EMIF |
1 32-Bit |
| External Memory Type Supported |
Async SRAM,SBSRAM,SDRAM |
| DMA (Ch) |
4-Ch |
| PCI |
1 32-Bit |
| McBSP |
2 |
| Timers |
2 32-Bit GP |
| Core Supply (Volts) |
1.5 V |
| IO Supply (V) |
3.3 V |
| Operating Temperature Range (°C) |
0 to 90,-40 to 105 |
| Rating |
Catalog |
TMS320C6205-200 特性
- High-Performance Fixed-Point Digital Signal Processor (DSP)- TMS320C6205
- 5-ns Instruction Cycle Time
- 200-MHz Clock Rate
- Eight 32-Bit Instructions/Cycle
- 1600 MIPS
- VelociTI™ Advanced-Very-Long-Instruction-Word (VLIW) TMS320C62x™ DSP Core
- Eight Highly Independent Functional Units:
- Six ALUs (32-/40-Bit)
- Two 16-Bit Multipliers (32-Bit Result)
- Load-Store Architecture With 32 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Instruction Set Features
- Byte-Addressable (8-, 16-, 32-Bit Data)
- 8-Bit Overflow Protection
- Saturation
- Bit-Field Extract, Set, Clear
- Bit-Counting
- Normalization
- 1M-Bit On-Chip SRAM
TMS320C6205-200 芯片订购指南
TMS320C6205-200 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| TMS320C6205DGHK200 |
TBD |
SNPB |
Level-3-220C-168 HR |
TMS320C6205DGHK200 |
TMS320C6205DGHK200 |
| TMS320C6205DZHK200 |
Green (RoHS & no Sb/Br) |
SNAGCU |
Level-3-260C-168 HR |
TMS320C6205DZHK200 |
TMS320C6205DZHK200 |
| TMS320C6205GHK200 |
TBD |
SNPB |
Level-3-220C-168 HR |
TMS320C6205GHK200 |
TMS320C6205GHK200 |
| TMS320C6205GHKA200 |
TBD |
SNPB |
Level-3-220C-168 HR |
TMS320C6205GHKA200 |
TMS320C6205GHKA200 |
| TMS320C6205ZHK200 |
Green (RoHS & no Sb/Br) |
SNAGCU |
Level-3-260C-168 HR |
TMS320C6205ZHK200 |
TMS320C6205ZHK200 |
| TMS32C6205DGHKA200 |
TBD |
SNPB |
Level-3-220C-168 HR |
TMS32C6205DGHKA200 |
TMS32C6205DGHKA200 |
| TMS32C6205DZHKA200 |
Green (RoHS & no Sb/Br) |
SNAGCU |
Level-3-260C-168 HR |
TMS32C6205DZHKA200 |
TMS32C6205DZHKA200 |
TMS320C6205-200 应用技术支持与电子电路设计开发资源下载
- TMS320C6205-200 数据资料 dataSheet 下载.PDF
- TI 德州仪器数字信号处理器 (DSP) & ARM 微处理器选型与价格 . xls
- OMAP-L13x/AM1x Linux PSP Overview
- ARM Assembly Language Tools v4.7 User's Guide
- ARM Optimizing C/C++ Compiler v4.7 User's Guide
- Power Management for AM18xx/AM17xx Processors
- ARM Portfolio Technical Overview Brochure
- Software and Hardware Design Challenges due to Dynamic Raw NAND Market
- Programmable Real-Time Unit (PRU): Extending Functionality Of Existing SoCs
TMS320C6205-200 工具与软件
