TMS320C6411-300 定点数字信号处理器
The TMS320C64x™ DSPs (including the TMS320C6411 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C6411 (C6411) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelocTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.
With performance of up to 2400 million instructions per second (MIPS) at a clock rate of 300 MHz, the C6411 device offers cost-effective solutions to high-performance DSP programming challenges. The C6411 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors
|
TMS320C6411-300 |
| CPU |
1 C64x |
| Peak MMACS |
2400 |
| Frequency (MHz) |
300 |
| RAM (KB) |
2 MB |
| On-Chip L1/SRAM |
32 KB |
| On-Chip L2/SRAM |
256 KB |
| EMIF |
1 32-Bit |
| External Memory Type Supported |
Async SRAM,SDRAM,SBSRAM |
| DMA (Ch) |
64-Ch EDMA |
| PCI |
1 32-Bit |
| HPI |
1 32/16-Bit |
| McBSP |
2 |
| Trace Enabled |
Yes |
| Timers |
3 32-Bit GP |
| Core Supply (Volts) |
1.2 V |
| IO Supply (V) |
3.3 V |
| Operating Temperature Range (°C) |
0 to 90 |
TMS320C6411-300 特性
- Low-Cost, High-Performance Fixed-Point DSP – TMS320C6411
- 3.33-ns Instruction Cycle Time
- 300-MHz Clock Rate
- Eight 32-Bit Instructions/Cycle
- Twenty-Eight Operations/Cycle
- 2400 MIPS
- Fully Software-Compatible With TMS320C62x™
- VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
- Eight Highly Independent Functional Units With VelociTI™ Extensions:
- Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
- Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
- Non-Aligned Load-Store Architecture
- 64 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Instruction Set Features
- Byte-Addressable (8-/16-/32-/64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
TMS320C6411-300 芯片订购指南
TMS320C6411-300 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| TMS320C6411AGLZ |
TBD |
SNPB |
Level-4-220C-72 HR |
TMS320C6411AGLZ |
TMS320C6411AGLZ |
| TMS320C6411AZLZ |
Pb-Free (RoHS Exempt) |
SNAGCU |
Level-4-260C-72HR |
TMS320C6411AZLZ |
TMS320C6411AZLZ |
TMS320C6411-300 应用技术支持与电子电路设计开发资源下载
- TMS320C6411-300 数据资料 dataSheet 下载.PDF
- TI 德州仪器数字信号处理器 (DSP) & ARM 微处理器选型与价格 . xls
- OMAP-L13x/AM1x Linux PSP Overview
- ARM Assembly Language Tools v4.7 User's Guide
- ARM Optimizing C/C++ Compiler v4.7 User's Guide
- Power Management for AM18xx/AM17xx Processors
- ARM Portfolio Technical Overview Brochure
- Software and Hardware Design Challenges due to Dynamic Raw NAND Market
- Programmable Real-Time Unit (PRU): Extending Functionality Of Existing SoCs
TMS320C6411-300 工具与软件
