TMS320C6418-500 定点数字信号处理器
The TMS320C64x™ DSPs (including the TMS320C6418 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C6418 (C6418) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI). The high-performance, lower-cost C6418 DSP enables customers to reduce system costs for telecom, software radio, Digital Terrestrial Television Broadcasting (DTTB), and digital Broadcast Satellite/Communication Satellite (BS/CS) applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.
With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C6418 device offers cost-effective solutions to high-performance DSP programming challenges
|
TMS320C6418-500 |
TMS320C6418-600 |
| CPU |
1 C64x |
1 C64x |
| Peak MMACS |
4000 |
4800 |
| Frequency (MHz) |
500 |
600 |
| On-Chip L1/SRAM |
32 KB |
32 KB |
| On-Chip L2/SRAM |
512 KB |
512 KB |
| EMIF |
1 32-Bit |
1 32-Bit |
| External Memory Type Supported |
Async SRAM,SDRAM,SBSRAM |
Async SRAM,SDRAM,SBSRAM |
| DMA (Ch) |
64-Ch EDMA |
64-Ch EDMA |
| HPI |
1 32/16-Bit |
1 32/16-Bit |
| McBSP |
2 |
2 |
| I2C |
2 |
2 |
| McASP |
2 |
2 |
| Trace Enabled |
Yes |
Yes |
| Timers |
3 32-Bit GP |
3 32-Bit GP |
| Hardware Accelerators |
VCP |
VCP |
| Core Supply (Volts) |
1.2 V |
1.4 V |
| IO Supply (V) |
3.3 V |
3.3 V |
| Operating Temperature Range (°C) |
-40 to 105 |
0 to 90 |
TMS320C6418-500 特性
- High-Performance Fixed-Point Digital Signal Processor (TMS320C6418)
- Commercial Temperature Device
- 1.67-ns Instruction Cycle Time
- 600-MHz Clock Rate
- 4800 MIPS
- Extended Temperature Device
- 2-ns Instruction Cycle Time
- 500-MHz Clock Rate
- 4000 MIPS
- Eight 32-Bit Instructions/Cycle
- Fully Software-Compatible With C64x™
- VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
- Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
- Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
- Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
- Load-Store Architecture With Non-Aligned Support
- 64 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Instruction Set Features
TMS320C6418-500 芯片订购指南
TMS320C6418-500 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| TMS320C6418GTS600 |
TBD |
SNPB |
Level-4-220C-72 HR |
TMS320C6418GTS600 |
TMS320C6418GTS600 |
| TMS320C6418GTSA500 |
TBD |
SNPB |
Level-4-220C-72 HR |
TMS320C6418GTSA500 |
TMS320C6418GTSA500 |
| TMS320C6418ZTS600 |
Pb-Free (RoHS Exempt) |
SNAGCU |
Level-4-260C-72HR |
TMS320C6418ZTS600 |
TMS320C6418ZTS600 |
| TMS320C6418ZTSA500 |
Pb-Free (RoHS Exempt) |
SNAGCU |
Level-4-260C-72HR |
TMS320C6418ZTSA500 |
TMS320C6418ZTSA500 |
TMS320C6418-500 应用技术支持与电子电路设计开发资源下载
- TMS320C6418-500 数据资料 dataSheet 下载.PDF
- TI 德州仪器数字信号处理器 (DSP) & ARM 微处理器选型与价格 . xls
- OMAP-L13x/AM1x Linux PSP Overview
- ARM Assembly Language Tools v4.7 User's Guide
- ARM Optimizing C/C++ Compiler v4.7 User's Guide
- Power Management for AM18xx/AM17xx Processors
- ARM Portfolio Technical Overview Brochure
- Software and Hardware Design Challenges due to Dynamic Raw NAND Market
- Programmable Real-Time Unit (PRU): Extending Functionality Of Existing SoCs
TMS320C6418-500 工具与软件
