TMS320C6452-900 数字信号处理器
The TMS320C64x+™ DSPs (including the TMS320C6452 device is the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The C6452 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices.
Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.
|
TMS320C6452-720 |
TMS320C6452-900 |
| CPU |
1 C64x+ |
1 C64x+ |
| Peak MMACS |
5760 |
7200 |
| Frequency (MHz) |
720 |
900 |
| On-Chip L1/SRAM |
64 KB |
64 KB |
| On-Chip L2/SRAM |
1408 KB |
1408 KB |
| EMIF |
1 16-Bit EMIFA,1 32-Bit DDR2 EMIF |
1 16-Bit EMIFA,1 32-Bit DDR2 EMIF |
| External Memory Type Supported |
Async SRAM,SBSRAM,DDR2SDRAM |
Async SRAM,SBSRAM,DDR2SDRAM |
| DMA (Ch) |
64-Ch EDMA |
64-Ch EDMA |
| EMAC |
10/100/1000 |
10/100/1000 |
| PCI |
1 32-Bit [66/33 MHz] |
1 32-Bit [66/33 MHz] |
| HPI |
1 32/16-Bit |
1 32/16-Bit |
| McASP |
1 |
1 |
| SPI |
1 |
1 |
| TSIP |
2 |
2 |
| UART (SCI) |
1 |
1 |
| I2C |
1 |
1 |
| VLYNQ |
1 |
1 |
| Trace Enabled |
Yes |
Yes |
| Timers |
4 64-Bit GP |
4 64-Bit GP |
| Core Supply (Volts) |
1.2 V |
1.2 V |
| IO Supply (V) |
3.3 V, 1.8 V, 1.2 V |
3.3 V, 1.8 V, 1.2 V |
| Operating Temperature Range (°C) |
0 to 90 |
0 to 90 |
TMS320C6452-900 特性
- High-Performance Digital Media Processor
- 720-MHz, 900-MHz C64x+™ Clock Rates
- 1.39 ns (-720), 1.11 ns (-900) Instruction Cycle Time
- 5760, 7200 MIPS
- Eight 32-Bit C64x+ Instructions/Cycle
- Fully Software-Compatible With C64x/Debug
- Commercial Temperature Ranges (-720, -900 only)
- Industrial Temperature Ranges (-720, -900 only)
- VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
- Eight Highly Independent Functional Units With VelociTI.2 Extensions:
- Six ALUs (32-/40-Bit), Each Supports Single 32-bit, Dual 16-bit, or Quad 8-bit Arithmetic per Clock Cycle
- Two Multipliers Support Four 16 x 16-bit Multiplies (32-bit Results) per Clock Cycle or Eight 8 x 8-bit Multiplies (16-Bit Results) per Clock Cycle
- Load-Store Architecture With Non-Aligned Support
- 64 32-bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Additional C64x+™ Enhancements
- Protected Mode Operation
- Exceptions Support for Error Detection and Program Redirection
- Hardware Support for Modulo Loop Auto-Focus Module Operation
TMS320C6452-900 芯片订购指南
TMS320C6452-900 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| TMS320C6452ZUT7 |
Pb-Free (RoHS Exempt) |
SNAGCU |
Level-4-245C-72HR |
TMS320C6452ZUT7 |
TMS320C6452ZUT7 |
| TMS320C6452ZUT9 |
Pb-Free (RoHS Exempt) |
SNAGCU |
Level-4-245C-72HR |
TMS320C6452ZUT9 |
TMS320C6452ZUT9 |
TMS320C6452-900 应用技术支持与电子电路设计开发资源下载
- TMS320C6452-900 数据资料 dataSheet 下载.PDF
- TI 德州仪器数字信号处理器 (DSP) & ARM 微处理器选型与价格 . xls
- OMAP-L13x/AM1x Linux PSP Overview
- ARM Assembly Language Tools v4.7 User's Guide
- ARM Optimizing C/C++ Compiler v4.7 User's Guide
- Power Management for AM18xx/AM17xx Processors
- ARM Portfolio Technical Overview Brochure
- Software and Hardware Design Challenges due to Dynamic Raw NAND Market
- Programmable Real-Time Unit (PRU): Extending Functionality Of Existing SoCs
TMS320C6452-900 工具与软件
