TMS320DM641 视频/影像定点数字信号处理器
The TMS320C64x™ DSPs (including the TMS320DM641 and TMS320DM640 devices) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320DM641 (DM641) and TMS320DM640 (DM640) devices are based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.
With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the DM641 device offers cost-effective solutions to high-performance DSP programming challenges
|
TMS320DM641 |
Applications |
Automotive,Video and Imaging |
Operating Systems |
DSP/BIOS |
DSP |
1 C64x |
DSP Instruction Type |
Fixed Point |
DSP MHz (Max.) |
500 |
DSP Peak MMACS |
4000 |
Video Capability |
Decode,Encode,Multi-Channel,Analytics |
TI Video Codecs |
JPEG,MPEG2,MPEG4-SP,MPEG4-ASP,VC1,H.264-BP,H.264-MP/HP |
Video Resolution/Frame Rate |
D1 or Less |
TI Audio Codecs |
G.711,MP3,AAC-LC,HE-AAC,AAC-LD |
On-Chip L1 Cache |
32 KB (DSP) |
On-Chip L2 Cache |
128 KB (DSP) |
General Purpose Memory |
Async SRAM,SBSRAM |
DRAM |
1 64-bit SDRAM |
EMAC |
10/100 |
I2C |
1 |
HPI |
1 |
McBSP |
2 |
McASP |
1 |
DMA (Ch) |
Yes |
Video Port (Configurable) |
2 8-Bit Single-Ch |
IO Supply (V) |
3.3 |
Trace Enabled |
Yes |
Pin/Package |
548FC/CSP, 548FCBGA |
TMS320DM641 特性
- High-Performance Digital Media Processor (TMS320DM641/TMS320DM640)
- 2.5-, 2-, 1.67-ns Instruction Cycle Time
- 400-, 500-, 600-MHz Clock Rate
- Eight 32-Bit Instructions/Cycle
- 3200, 4000, 4800 MIPS
- Fully Software-Compatible With C64x™
- VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word VLIW) TMS320C64x™ DSP Core
- Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
- Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
- Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
- Load-Store Architecture With Non-Aligned Support
- 64 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Instruction Set Features
- Byte-Addressable (8-/16-/32-/64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- VelociTI.2™ Increased Orthogonality
TMS320DM641 芯片订购指南
TMS320DM641 质量与无铅数据
器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
TMS320DM641AGDK5 |
TBD |
SNPB |
Level-4-220C-72 HR |
TMS320DM641AGDK5 |
TMS320DM641AGDK5 |
TMS320DM641AGDK6 |
TBD |
SNPB |
Level-4-220C-72 HR |
TMS320DM641AGDK6 |
TMS320DM641AGDK6 |
TMS320DM641AGNZ5 |
TBD |
SNPB |
Level-4-220C-72 HR |
TMS320DM641AGNZ5 |
TMS320DM641AGNZ5 |
TMS320DM641AGNZ6 |
TBD |
SNPB |
Level-4-220C-72 HR |
TMS320DM641AGNZ6 |
TMS320DM641AGNZ6 |
TMS320DM641AGNZA5 |
TBD |
SNPB |
Level-4-220C-72 HR |
TMS320DM641AGNZA5 |
TMS320DM641AGNZA5 |
TMS320DM641AZDK5 |
Pb-Free (RoHS Exempt) |
SNAGCU |
Level-4-260C-72HR |
TMS320DM641AZDK5 |
TMS320DM641AZDK5 |
TMS320DM641AZDK6 |
Pb-Free (RoHS Exempt) |
SNAGCU |
Level-4-260C-72HR |
TMS320DM641AZDK6 |
TMS320DM641AZDK6 |
TMS320DM641AZNZ6 |
Pb-Free (RoHS Exempt) |
SNAGCU |
Level-4-260C-72HR |
TMS320DM641AZNZ6 |
TMS320DM641AZNZ6 |
TMS320DM641AZNZA5 |
Pb-Free (RoHS Exempt) |
SNAGCU |
Level-4-260C-72HR |
TMS320DM641AZNZA5 |
TMS320DM641AZNZA5 |
TMS320DM641 应用技术支持与电子电路设计开发资源下载
- TMS320DM641 数据资料 dataSheet 下载.PDF
- TI 德州仪器数字信号处理器 (DSP) & ARM 微处理器选型与价格 . xls
- OMAP-L13x/AM1x Linux PSP Overview
- ARM Assembly Language Tools v4.7 User's Guide
- ARM Optimizing C/C++ Compiler v4.7 User's Guide
- Power Management for AM18xx/AM17xx Processors
- ARM Portfolio Technical Overview Brochure
- Software and Hardware Design Challenges due to Dynamic Raw NAND Market
- Programmable Real-Time Unit (PRU): Extending Functionality Of Existing SoCs
TMS320DM641 工具与软件