TMS320VC5501 定点数字信号处理器
The TMS320VC5501 (5501) fixed-point digital signal processor (DSP) is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform data transfers independent of the CPU activity.
The C55x™ CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit × 17-bit multiplication in a single cycle.
|
TMS320VC5501 |
| Applications |
Audio,Automotive,Communications and Telecom,Consumer Electronics,Industrial |
| Operating Systems |
DSP/BIOS,VLX |
| DSP |
1 C55x |
| DSP Instruction Type |
Fixed Point |
| DSP MHz (Max.) |
300 |
| DSP Peak MMACS |
600 |
| On-Chip L1 Cache |
16 KB |
| General Purpose Memory |
1 32-bit (Async SRAM, SBSRAM) |
| DRAM |
SDRAM |
| UART (SCI) |
1 |
| I2C |
1 |
| HPI |
1 8-bit HPI |
| McBSP |
2 |
| DMA (Ch) |
6-Ch DMA |
| IO Supply (V) |
3.3 |
| Operating Temperature Range (C) |
-40 to 85 |
| Pin/Package |
176LQFP, 201BGA MICROSTAR |
| Approx. Price (US$) |
4.50 | 1ku |
TMS320VC5501 特性
- High-Performance, Low-Power, Fixed-Point TMS320C55x™ Digital Signal Processor (DSP)
- 3.33-ns Instruction Cycle Time for 300-MHz Clock Rate
- 16K-Byte Instruction Cache (I-Cache)
- One/Two Instructions Executed per Cycle
- Dual Multipliers [Up to 600 Million Multiply-Accumulates Per Second (MMACS)]
- Two Arithmetic/Logic Units (ALUs)
- One Program Bus, Three Internal Data/Operand Read Buses, and Two Internal Data/Operand Write Buses
- Instruction Cache (16K Bytes)
- 16K × 16-Bit On-Chip RAM That is Composed of Four Blocks of 4K × 16-Bit Dual-Access RAM (DARAM) (32K Bytes)
- 16K × 16-Bit One-Wait-State On-Chip ROM (32K Bytes)
- 8M × 16-Bit Maximum Addressable External Memory Space
- 32-Bit External Parallel Bus Memory Supporting External Memory Interface (EMIF) With General-Purpose Input/Output (GPIO) Capabilities and Glueless Interface to:
- Asynchronous Static RAM (SRAM)
- Asynchronous EPROM
- Synchronous DRAM (SDRAM)
- Synchronous Burst RAM (SBRAM)
- Emulation/Debug Trace Capability Saves Last 16 Program Counter (PC) Discontinuities and Last 32 PC Values
- Programmable Low-Power Control of Six Device Functional Domains
- On-Chip Peripherals
- Six-Channel Direct Memory Access (DMA) Controller
TMS320VC5501 芯片订购指南
TMS320VC5501 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| TMS320VC5501GZZ300 |
TBD |
SNPB |
Level-3-220C-168 HR |
TMS320VC5501GZZ300 |
TMS320VC5501GZZ300 |
| TMS320VC5501PGF300 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-4-260C-72 HR |
TMS320VC5501PGF300 |
TMS320VC5501PGF300 |
| TMS320VC5501ZZZ300 |
Green (RoHS & no Sb/Br) |
SNAGCU |
Level-3-260C-168 HR |
TMS320VC5501ZZZ300 |
TMS320VC5501ZZZ300 |
TMS320VC5501 应用技术支持与电子电路设计开发资源下载
- TMS320VC5501 数据资料 dataSheet 下载.PDF
- TI 德州仪器数字信号处理器 (DSP) & ARM 微处理器选型与价格 . xls
- OMAP-L13x/AM1x Linux PSP Overview
- ARM Assembly Language Tools v4.7 User's Guide
- ARM Optimizing C/C++ Compiler v4.7 User's Guide
- Power Management for AM18xx/AM17xx Processors
- ARM Portfolio Technical Overview Brochure
- Software and Hardware Design Challenges due to Dynamic Raw NAND Market
- Programmable Real-Time Unit (PRU): Extending Functionality Of Existing SoCs
TMS320VC5501 工具与软件
