TMS320VC5510A 定点数字信号处理器
The TMS320VC5510/5510A (5510/5510A) fixed-point digital signal processors (DSPs) are based on the TMS320C55x DSP generation CPU processor core. The C55x™;DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity.
The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication in a single cycle
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TMS320VC5510A |
| Applications |
Audio,Automotive,Communications and Telecom,Consumer Electronics,Industrial |
| Operating Systems |
DSP/BIOS,VLX |
| DSP |
1 C55x |
| DSP Instruction Type |
Fixed Point |
| DSP MHz (Max.) |
160,200 |
| DSP Peak MMACS |
320,400 |
| On-Chip L1 Cache |
24 KB |
| General Purpose Memory |
1 32-bit (Async SRAM, SBSRAM) |
| DRAM |
SDRAM |
| HPI |
1 16-bit HPI |
| McBSP |
3 |
| DMA (Ch) |
6-Ch DMA |
| IO Supply (V) |
3.3 |
| Operating Temperature Range (C) |
-40 to 85,0 to 85 |
| Pin/Package |
205BGA MICROSTAR, 240BGA MICROSTAR |
| Approx. Price (US$) |
14.40 | 1ku |
TMS320VC5510A 特性
- High-Performance, Low-Power, Fixed-Point TMS320C55x™; Digital Signal Processor (DSP)
- 6.25-/5-ns Instruction Cycle Time
- 160-/200-MHz Clock Rate
- One/Two Instructions Executed per Cycle
- Dual Multipliers (Up to 400 Million Multiply-Accumulates Per Second (MMACS))
- Two Arithmetic/Logic Units
- One Internal Program Bus
- Three Internal Data/Operand Read Buses
- Two Internal Data/Operand Write Buses
- Instruction Cache (24K Bytes)
- 160K x 16-Bit On-Chip RAM Composed of:
- Eight Blocks of 4K × 16-Bit Dual-Access RAM (DARAM) (64K Bytes)
- 32 Blocks of 4K × 16-Bit Single-Access RAM (SARAM)(256K Bytes)
- 16K × 16-Bit On-Chip ROM (32K Bytes)
- 8M × 16-Bit Maximum Addressable External Memory Space
- 32-Bit External Memory Interface (EMIF) With Glueless Interface to:
- Asynchronous Static RAM (SRAM)
- Asynchronous EPROM
- Synchronous DRAM (SDRAM)
- Synchronous Burst SRAM (SBSRAM)
TMS320VC5510A 芯片订购指南
TMS320VC5510A 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| TMS320VC5510AGGW1 |
TBD |
SNPB |
Level-3-220C-168 HR |
TMS320VC5510AGGW1 |
TMS320VC5510AGGW1 |
| TMS320VC5510AGGW2 |
TBD |
SNPB |
Level-3-220C-168 HR |
TMS320VC5510AGGW2 |
TMS320VC5510AGGW2 |
| TMS320VC5510AGGWA1 |
TBD |
SNPB |
Level-3-220C-168 HR |
TMS320VC5510AGGWA1 |
TMS320VC5510AGGWA1 |
| TMS320VC5510AGGWA2 |
TBD |
SNPB |
Level-3-220C-168 HR |
TMS320VC5510AGGWA2 |
TMS320VC5510AGGWA2 |
| TMS320VC5510AZGW1 |
Green (RoHS & no Sb/Br) |
SNAGCU |
Level-3-260C-168 HR |
TMS320VC5510AZGW1 |
TMS320VC5510AZGW1 |
| TMS320VC5510AZGW2 |
Green (RoHS & no Sb/Br) |
SNAGCU |
Level-3-260C-168 HR |
TMS320VC5510AZGW2 |
TMS320VC5510AZGW2 |
| TMS320VC5510AZGWA1 |
Green (RoHS & no Sb/Br) |
SNAGCU |
Level-3-260C-168 HR |
TMS320VC5510AZGWA1 |
TMS320VC5510AZGWA1 |
| TMS320VC5510AZGWA2 |
Green (RoHS & no Sb/Br) |
SNAGCU |
Level-3-260C-168 HR |
TMS320VC5510AZGWA2 |
TMS320VC5510AZGWA2 |
TMS320VC5510A 应用技术支持与电子电路设计开发资源下载
- TMS320VC5510A 数据资料 dataSheet 下载.PDF
- TI 德州仪器数字信号处理器 (DSP) & ARM 微处理器选型与价格 . xls
- OMAP-L13x/AM1x Linux PSP Overview
- ARM Assembly Language Tools v4.7 User's Guide
- ARM Optimizing C/C++ Compiler v4.7 User's Guide
- Power Management for AM18xx/AM17xx Processors
- ARM Portfolio Technical Overview Brochure
- Software and Hardware Design Challenges due to Dynamic Raw NAND Market
- Programmable Real-Time Unit (PRU): Extending Functionality Of Existing SoCs
TMS320VC5510A 工具与软件
