UC1825A-SP 高速 PWM 控制器

The UC1825A PWM controller is an improved version of the standard UC1825 family. Performance enhancements have been made to several of the circuit blocks. Error amplifier gain bandwidth product is 12 MHz, while input offset voltage is 2 mV. Current limit threshold is assured to a tolerance of 5%. Oscillator discharge current is specified at 10 mA for accurate dead time control. Frequency accuracy is improved to 6%. Startup supply current, typically 100 µA, is ideal for off-line applications. The output drivers are redesigned to actively sink current during UVLO at no expense to the startup current specification. In addition each output is capable of 2-A peak currents during transitions.

Functional improvements have also been implemented in this family

UC1825A-SP
Control Method Current    
Duty Cycle (Max) (%) 50    
Frequency (Max) (kHz) 1000    
UVLO Thresholds On/Off (V) 9.2/8.4    
Pin/Package 16CDIP, 20LCCC
Regulated Outputs (#) 2    
Operating Temperature Range (C) -55 to 125    
Rating Space
UC1825A-SP 特性
UC1825A-SP 芯片订购指南
器件 状态 温度 (oC) 价格(美元) 封装 | 引脚 封装数量 | 封装载体 丝印标记
5962-8768102V2A ACTIVE -55 to 125 299.06 | 100u LCCC (FK) | 20 1 | TUBE  
5962-8768102VEA ACTIVE -55 to 125 347.13 | 100u CDIP (J) | 16 1 | TUBE  
5962-8768105VEA ACTIVE -55 to 125 358.05 | 100u CDIP (J) | 16 1 | TUBE  
UC1825A-SP 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
5962-8768102V2A TBD   POST-PLATE   N/A for Pkg Type 5962-8768102V2A 5962-8768102V2A
5962-8768102VEA TBD   A42   N/A for Pkg Type 5962-8768102VEA 5962-8768102VEA
5962-8768105VEA TBD   A42   N/A for Pkg Type 5962-8768105VEA 5962-8768105VEA
UC1825A-SP 工具与软件
培训内容 型号 软件/工具类型
最常用开关模式电源的功率级设计器 POWERSTAGE-DESIGNER Texas Instruments
UC1825A-SP 应用技术支持与电子电路设计开发资源下载
  1. UC1825A-SP数据资料 dataSheet 下载.PDF
  2. TI 德州仪器电源管理选型与价格参考 . xls