LAN9118

Please consider this device

The LAN9118 is a full-featured, single-chip 10/100 Ethernet controller designed for embedded applications where performance, flexibility, ease of integration and system cost control are required. The LAN9118 has been specifically architected to provide the highest performance possible for any given architecture. The LAN9118 is fully IEEE 802.3 10BASE-T and 802.3u 100BASE-TX compliant.

The LAN9118 includes an integrated Ethernet MAC and PHY with a high-performance SRAM-like slave interface. The simple, yet highly functional host bus interface provides a glue-less connection to most common 16-bit and 32-bit microprocessors and microcontrollers. LAN9118 includes large transmit and receive data FIFOs with a high-speed host bus interface to accommodate high bandwidth, high latency applications. In addition, the LAN9118 memory buffer architecture allows the most efficient use of memory resources by optimizing packet granularity.

Features
  • Optimized for the highest-data rate applications such as high-definition video and multi-media applications
  • Efficient architecture with low CPU overhead
  • Easily interfaces to most 32-bit and 16-bit Embedded CPU’s
  • Integrated PHY
  • Supports audio & video streaming over Ethernet: multiple high-definition (HD) MPEG2 streams
  • Pin compatible with other members of LAN9118 Family (LAN9117, LAN9116 and LAN9115)
  • Video distribution systems, multi-room PVR
  • High-end Cable, satellite, and IP set-top boxes
  • Digital video recorders
  • High definition televisions
  • Digital media clients/servers
  • Home gateways
  • Supports highest performance applications Highest performing non-PCI Ethernet controller in the market 32-bit interface with fast bus cycle times Burst-mode read support
  • Highest performing non-PCI Ethernet controller in the market
  • 32-bit interface with fast bus cycle times
  • Burst-mode read support
  • Eliminates dropped packets Internal buffer memory can store over 200 packets Supports automatic or host-triggered PAUSE and back-pressure flow control
  • Internal buffer memory can store over 200 packets
  • Supports automatic or host-triggered PAUSE and back-pressure flow control
  • Minimizes CPU overhead Supports Slave-DMA Interrupt Pin with Programmable Hold-off timer
  • Supports Slave-DMA
  • Interrupt Pin with Programmable Hold-off timer
  • Reduces system cost and increases design flexibility SRAM-like interface easily interfaces to most Embedded CPU's or SoC's Low-cost, low-pin count non-PCI interface for embedded designs
  • SRAM-like interface easily interfaces to most Embedded CPU's or SoC's
  • Low-cost, low-pin count non-PCI interface for embedded designs
  • Reduced-Power Modes Numerous power management modes Wake on LAN* Magic packet wakeup* Wakeup indicator event signal Link Status Change
  • Numerous power management modes
  • Wake on LAN*
  • Magic packet wakeup*
  • Wakeup indicator event signal
  • Link Status Change
  • Single chip Ethernet controller Fully compliant with IEEE 802.3/802.3u standards Integrated Ethernet MAC and PHY 10BASE-T and 100BASE-TX support Full- and Half-duplex support Full-duplex flow control Backpressure for half-duplex flow control Preamble generation and removal Automatic 32-bit CRC generation and checking Automatic payload padding and pad removal Loop-back modes
  • Fully compliant with IEEE 802.3/802.3u standards
  • Integrated Ethernet MAC and PHY
  • 10BASE-T and 100BASE-TX support
  • Full- and Half-duplex support
  • Full-duplex flow control
  • Backpressure for half-duplex flow control
  • Preamble generation and removal
  • Automatic 32-bit CRC generation and checking
  • Automatic payload padding and pad removal
  • Loop-back modes
  • Flexible address filtering modes One 48-bit perfect address 64 hash-filtered multicast addresses Pass all multicast Promiscuous mode Inverse filtering Pass all incoming with status report Disable reception of broadcast packets
  • One 48-bit perfect address
  • 64 hash-filtered multicast addresses
  • Pass all multicast
  • Promiscuous mode
  • Inverse filtering
  • Pass all incoming with status report
  • Disable reception of broadcast packets
  • Integrated Ethernet PHY Auto-negotiation Automatic polarity detection and correction
  • Auto-negotiation
  • Automatic polarity detection and correction
  • High-Performance host bus interface Simple, SRAM-like interface 32/16-bit data bus Large, 16Kbyte FIFO memory that can be allocated to RX or TX functions One configurable host interrupt
  • Simple, SRAM-like interface
  • 32/16-bit data bus
  • Large, 16Kbyte FIFO memory that can be allocated to RX or TX functions
  • One configurable host interrupt
  • Miscellaneous features Low profile 100-pin, TQFP RoHS Compliant package Integral 1.8V regulator General Purpose Timer Support for optional EEPROM Support for 3 status LEDs multiplexed with Programmable GPIO signals
  • Low profile 100-pin, TQFP RoHS Compliant package
  • Integral 1.8V regulator
  • General Purpose Timer
  • Support for optional EEPROM
  • Support for 3 status LEDs multiplexed with Programmable GPIO signals
  • 3.3V Power Supply with 5V tolerant I/O
  • 0° to 70°C
Parameter
Parameter Name Value Value
Description 10Based-T/100Based-TX Ethernet Controller with 16/32 bit interface 10Based-T/100Based-TX Ethernet Controller with 16/32 bit interface
Ethernet Bandwidth 10Base-T/ 100Base-TX 10Base-T/ 100Base-TX
MAC Yes Yes
PHY Yes Yes
TX/RX RAM Buffer(Bytes) 16K 16K
Interrupt Pin 1 1
LEDs 3 3
Op. Voltage (V) 3.3 3.3
# Ethernet Ports 1 1
Temp. Range Max. (°C) 70 70
Mixed Endian Yes Yes
Interface1 16-bit or 32-bit 16-bit or 32-bit
Vdd I/O (V) 3.3 3.3
Documents
LAN9118 High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller Data ShData Sheets07/11/20081445KB
AN12.10 - LAN9118 Power Consumption ValuesAppNote04/25/2014146KB
AN12.12 - LAN9118 Family Programmer Reference GuideAppNote12/15/2009561KB
AN12.19 - Designing for LAN9118 Family Footprint CompatibilityAppNote06/07/2005206KB
AN12.5 - Designing with the LAN9118 - Getting StartedAppNote01/29/2009963KB
AN14.10 - Migrating from the LAN9118 to the LAN9218IAppNote04/13/2006177KB
AN17.18 - SMSC Design Guide for Power over Ethernet ApplicationsAppNote09/20/2009445KB
AN2157 - Transient Protection in Power Over Ethernet ApplicationsAppNote05/24/2016229KB
AN24.16 - LAN9xxx Series MigrationAppNote04/25/2014422KB
AN8.13 - Suggested MagneticsAppNote06/28/2011240KB
LAN9118 IBIS ModelIBIS10/17/2006241KB
LAN91xx/LAN92xx uboot driver for ARMSoftware Library08/22/2008
LAN91xx/LAN92xx VxWorks 5.5 driver on SH3 processorSoftware Library04/14/2009
LAN91xx/LAN92xx/LAN9311/LAN9312 eBoot Driver for XScale ProcessorSoftware Library06/01/2007
LAN91xx/LAN92xx/LAN9311/LAN9312 Linux Driver on SH3 ProcessorSoftware Library08/22/2008
LAN91xx/LAN92xx/LAN9311/LAN9312 Linux driver on XScale processorSoftware Library08/22/2008
LAN91xx/LAN92xx/LAN9311/LAN9312 Windows CE 5.0 & 6.0 DriverSoftware Library01/29/2014
LAN9118 100-pin TQFP Package Component Placement ChecklistDesign Checklist03/15/200546KB
LAN9118 100-pin TQFP Package Routing ChecklistDesign Checklist03/15/200555KB
LAN9118 TQFP Rev E Schematic ChecklistDesign Checklist07/19/200778KB
LAN9118 High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller Data BrProduct Briefs07/11/2008117KB
LAN9118 Reference Design Bill of MaterialsSchematics06/20/200722KB
LAN9118 Reference Design SchematicSchematics07/09/200746KB
Ordering Information
Part NumberLeadsPackage TypeTemp RangePacking1+26+100+1000+5000+
LAN9118-MT100LQFP0C to +70CTRAY18.6415.5314.1213.6413.48
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RoHS Information
PartNumberDeviceWeightShippingWeightLeadCountPackageTypePackageWidthSolderCompositionJEDECIndicatorRoHSChinaEFUP
LAN9118-MT0.5804006.666667100LQFP14x14x1.6mmMatte Tine3
LAN9118-MT-D000.5804006.666667100LQFP14x14x1.6mmMatte Tine3
LAN9118-MT-DR10.5804006.666667100LQFP14x14x1.6mmMatte Tine3
LAN9118 High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller Data Sh LAN9118
AN12.10 LAN9118
AN12.12 LAN9118
AN12.19 LAN9118
AN12.5 LAN9118
AN14.10 LAN9118
AN17.18 LAN9313
AN2157 LAN9353
AN24.16 LAN9221
AN8.13 LAN9355
LAN9118 100-pin TQFP Package Component Placement Checklist LAN9118
LAN9118 100-pin TQFP Package Routing Checklist LAN9118
LAN9118 TQFP Rev E Schematic Checklist LAN9118
LAN9118 High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller Data Br LAN9118
LAN9118 Reference Design Bill of Materials LAN9118
LAN9118 Reference Design Schematic LAN9118