SN65LVCP204 2.5Gbps 4x4 交叉点交换器
The SN65LVCP204 is a 4×4 non-blocking crosspoint switch in a flow-through pinout that allows for ease in PCB layout. VML signaling is used to achieve a high-speed data throughput while using low power. Each of the output drivers includes a 4:1 multiplexer to allow any input to be routed to any output. Internal signal paths are fully differential to achieve high signaling speeds while maintaining low signal skews. The SN65LVCP204 incorporates 100-
termination resistors for those applications where board space is at a premium. Transmit preemphasis and receive equalization are built in for superior signal integrity performance
|
SN65LVCP202 |
SN65LVCP204 |
SN65LVCP22 |
SN65LVCP23 |
SN65LVCP402 |
SN65LVCP404 |
SN65LVDS122 |
SN65LVDS250 |
| No. of Rx |
2 |
4 |
2 |
2 |
2 |
4 |
2 |
4 |
| No. of Tx |
2 |
4 |
2 |
2 |
2 |
4 |
2 |
4 |
| Signaling Rate(Mbps) |
2500 |
2500 |
1000 |
1300 |
4250 |
4250 |
1500 |
2000 |
| Supply Voltage(s)(V) |
3.3 |
3.3 |
3.3 |
3.3 |
3.3 |
3.3 |
3.3 |
3.3 |
| ICC(Max)(mA) |
115 |
220 |
85 |
65 |
110 |
220 |
100 |
145 |
| Pin/Package |
24VQFN |
48VQFN |
16SOIC, 16TSSOP |
16SOIC, 16TSSOP |
24VQFN |
48VQFN |
16SOIC, 16TSSOP |
38TSSOP |
| Operating Temperature Range(°C) |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
-40 to 85 |
| Peak-to-Peak Jitter(Max)(ps) |
30 |
30 |
105 |
100 |
30 |
30 |
65 |
110 |
| Output Signal |
VML |
VML |
LVDS |
LVPECL |
VML |
VML |
LVDS |
LVDS |
| Input Signal |
CML,VML |
CML,VML |
CML, LVDS, LVPECL |
CML, LVDS, LVPECL |
CML,VML |
CML,VML |
CML, LVDS, LVPECL |
CML, LVDS, LVPECL |
| Part-to-Part Skew(Max)(ps) |
300 |
300 |
100 |
100 |
500 |
300 |
100 |
300 |
| Rx tpd(Typ)(ns) |
0.5 |
0.7 |
0.65 |
0.65 |
1 |
0.5 |
0.65 |
0.8 |
| Tx tpd(Typ)(ns) |
0.5 |
0.7 |
0.65 |
0.65 |
1 |
0.5 |
0.65 |
0.8 |
| ESD HBM(kV) |
4 |
3 |
5 |
5 |
3 |
3 |
4 |
3 |
| Approx. Price (US$) |
3.80 | 1ku |
6.00 | 1ku |
2.25 | 1ku |
4.00 | 1ku |
5.80 | 1ku |
9.00 | 1ku |
3.75 | 1ku |
6.75 | 1ku |
SN65LVCP204 特性
- Up to 2.5-Gbps Operation
- Nonblocking Architecture Allows Each
Output to Be Connected to Any Input
- 30 ps of Deterministic Jitter
- Selectable Transmit Preemphasis Per Lane
- Receive Equalization
- Available Packaging: 24-Pin QFN
- Propagation Delay Times: 500 ps Typical
- Inputs Electrically Compatible With
CML Signal Levels
- Operates From a Single 3.3-V Supply
- Outputs Can Be Driven to Hi-Z State
- Low Power: 290 mW (typ)
- Integrated Termination Resistors
- APPLICATIONS
- Clock Buffering/Clock MUXing
- Wireless Base Stations
- High-Speed Network Routing
- Telecom/Datacom
SN65LVCP204 芯片订购指南
| 器件 |
状态 |
温度 |
价格 |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| SN65LVCP204RGZR |
ACTIVE |
-40 to 85 |
6.00 | 1ku |
VQFN (RGZ) | 48 |
2500 | LARGE T&R |
LVCP204 |
| SN65LVCP204RGZT |
ACTIVE |
-40 to 85 |
6.90 | 1ku |
VQFN (RGZ) | 48 |
250 | SMALL T&R |
LVCP204 |
SN65LVCP204 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| SN65LVCP204RGZR |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-3-260C-168 HR |
SN65LVCP204RGZR |
SN65LVCP204RGZR |
| SN65LVCP204RGZT |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-3-260C-168 HR |
SN65LVCP204RGZT |
SN65LVCP204RGZT |
SN65LVCP204 应用技术支持与电子电路设计开发资源下载
- SN65LVCP204 数据资料 dataSheet 下载.PDF
- TI 德州仪器均衡器和转接驱动器选型与价格 . xls
- 所选封装材料的热学和电学性质 (PDF 645 KB)
- 接口选择指南 (Rev. D) (PDF 2994 KB)
- Signaling Rate vs. Distance for Differential Buffers (PDF 420 KB)
- Q1 2009 Issue Analog Applications Journal (slyt319.PDF, 1.39 MB)
- Isolated RS-485 Reference Design (PDF 80 KB)
- 无铅组件涂层的保存期评估 (PDF 1305 KB)
- Analog Signal Chain Guide (8.62 MB)
- Industrial Interface IC Solutions (101 KB)
