SN65LVDS84A Flatlink 发送器
When transmitting, data bits D0 - D20 are each loaded into registers of the 'LVDS84A upon the falling edge. The internal PLL is frequency-locked to CLKIN and then used to unload the data registers in 7-bit slices. The three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers
SN65LVDS84A
Number of Parallel Inputs
21
Data Throughput(MB/s)
197
Serial Data Transmitter Channels
3
Type of Line Circuit
LVDS
Driver (RL)(Ohms)
100
Supply Voltage(s)(V)
3.3
ICC(mA)
35
PLL Frequency(MHz)
31 - 75
Operating Temperature Range(°C)
-40 to 125
Pin/Package
48TSSOP
SN65LVDS84A 特性
21:3 Data Channel Compression at up to 196 Million Bytes per Second Throughput
Suited for SVGA, XGA, or SXGA Data Transmission From Controller to Display With Very Low EMI
21 Data Channels Plus Clock In Low-Voltage TTL Inputs and 3 Data Channels Plus Clock Out Low-Voltage Differential Signaling (LVDS) Outputs
Operates From a Single 3.3-V Supply and 89 mW (Typ)
Ultralow-Power 3.3-V CMOS Version of the SN75LVDS84. Power Consumption About One Third of the 'LVDS84
Packaged in Thin Shrink Small-Outline Package (TSSOP) With 20 Mil Terminal Pitch
Consumes Less Than 0.54 mW When Disabled
Wide Phase-Lock Input Frequency Range: 31 MHz to 75 MHz
No External Components Required for PLL
Outputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
SSC Tracking Capability of 3% Center Spread at 50-kHz Modulation Frequency
Improved Replacement for SN75LVDS84 and NSC's DS90CF363A 3-V Device
Available in Q-Temp Automotive
SN65LVDS84A 芯片订购指南
器件
状态
温度
价格
封装 | 引脚
封装数量 | 封装载体
丝印标记
SN65LVDS84AQDGG
ACTIVE
-40 to 125
2.70 | 1ku
TSSOP (DGG) | 48 40
SN65LVDS84AQDGGR
ACTIVE
-40 to 125
2.70 | 1ku
TSSOP (DGG) | 48 2000 | LARGE T&R
SN65LVDS84A 质量与无铅数据
器件
环保计划*
铅/焊球涂层
MSL 等级/回流焊峰
环保信息与无铅 (Pb-free)
DPPM / MTBF / FIT 率
SN65LVDS84AQDGG
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SN65LVDS84AQDGG
SN65LVDS84AQDGG
SN65LVDS84AQDGGR
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SN65LVDS84AQDGGR
SN65LVDS84AQDGGR
SN65LVDS84A 应用技术支持与电子电路设计开发资源下载
SN65LVDS84A 数据资料 dataSheet 下载 .PDF TI 德州仪器FlatLink选型与价格 . xls 所选封装材料的热学和电学性质 (PDF 645 KB)Q1 2009 Issue Analog Applications Journal (slyt319.PDF, 1.39 MB)使用 TI 的 SN65LVDS84A 收发器改善 CAN 网络安全性 (zhct033.PDF, 299 KB)Isolated CAN Reference Design (PDF 48 KB)Isolated RS-485 Reference Design (PDF 80 KB)无铅组件涂层的保存期评估 (PDF 1305 KB)Isolated CAN EVM User's Guide (PDF 1168 KB)Energy Harvesting: Solar Solutions Guide (PDF 409 KB)Analog Signal Chain Guide (8.62 MB)Industrial Interface IC Solutions (101 KB)
SN65LVDS84A 工具与软件
培训内容
型号
软件/工具类型
通过 CAN 总线进行工业控制的演示平台
CANBUS-DEMO 硬件参考设计
The SN75LVDS84A and SN65LVDS84AQ FlatLink transmitters contains three 7-bit parallel-load serial-out shift registers, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted over 3 balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 or SN75LVDS86/86A. 
