HMC905LP3E 6 GHz Low Noise Programmable Divider (N = 1 to 4) SMT
The HMC905LP3E is a SiGe BiCMOS low noise programmable frequency divider in a 3x3 mm leadless surface mount package. The circuit can be programmed to divide from N = 1 to N = 4 in the 400 MHz to 6 GHz input frequency range. The high level output power (up to 6 dBm single ended) with a very low SSB phase noise and 50% duty cycle makes this device ideal for low noise clock generation, LO generation and LO drive applications. Configurable bias and output power controls allow current consumption and output power control. The device incorporates a power down feature, good input to output isolation and fast start up time. The HMC905LP3E can be included into fast switching "ping-pong" applications.
技术特性
- Low Noise Floor: -164 dBc/Hz
at 10 MHz Offset for N = 4
- Programmable Frequency
Divider, N = 1, 2, 3 or 4
- Input Frequency Range:
400 MHz to 6 GHz
- Output Power up to +6 dBm
- Sleep Mode: Consumes <1 μA
- 16 Lead 3x3mm SMT Package: 9mm²
应用领域 APPLICATION
- LO Generation with Low Noise Floor
- Software Defined Radios
- Clock Generators
- Fast Switching Synthesizers
- Military Applications
- Test Equipment
- Sensors
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技术指标
| Input Freq. (GHz) |
Function |
Input Power (dBm) |
Output
Power (dBm) |
100 kHz SSB Phase Noise (dBc/Hz) |
Bias Supply |
Package |
| 0.4 - 6.0 |
Programmable Divider (N = 1 to 4) |
0 to +9 |
5 |
-158 |
+3.3V @ 100mA |
LP3 |
订购信息 Ordering Information
功能框图 Functional Block Diagram
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