领先的 FPGA 价格/性能/功耗
业界领先的系统解决方案Kintex-7 FPGA 能够以不同价位提供高信号处理能力和低功耗，从而满足长期演进 (LTE) 无线网络的部署要求。这些器件可以满足新一代高清 (HD) 3D 平板显示器严格的功耗与成本要求。 Kintex-7 系列也可提供新一代广播视频点播系统所需的串行带宽。
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产品优势
Kintex-7 文档资料
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| 描述 | 修改 | 大小 |
| DS180：7 Series FPGA Overview | ver 1.11 | 579 KB |
| DS181：Artix-7 FPGA Data Sheet: DC and Switching Characteristics | v1.3 | 1.03 MB |
| 描述 | 修改 | 大小 |
UG475：7 Series FPGA Packaging and Pinout Specifications。 This specification includes information on the Artix™-7, Kintex™-7, and Virtex®-7 device/package combinations and maximum I/Os, pin definitions, ASCII pinout files, and pinout diagrams showing I/O banks, power and ground placement, and memory groupings. |
ver 1.6 | 23.99 MB |
UG470：7 Series FPGA Configuration User Guide This all-encompassing configuration guide includes chapters on configuration interfaces, multi-bitstream management, bitstream encryption, boundary-scan and JTAG configuration, and reconfiguration techniques for Xilinx® 7 series FPGA. |
ver 1.4 | 4.26 MB |
| UG471：7 Series FPGA SelectIO Resources User Guide。
This guide describes the SelectIO™ resources available in the 7 series FPGA. |
ver 1.2 | 7.18 MB |
| UG472：7 Series FPGA Clocking Resources User Guide。
This guide serves as a technical reference describing the 7 series FPGA clocking resources. |
v1.5 | 4.11 MB |
| UG473：7 Series FPGA Memory Resources User Guide。
This guide describes the 7 Series FPGA block RAM and FIFO capabilities. |
ver 1.6 | 2.74 MB |
| UG474：7 Series FPGA Configurable Logic Block User Guide。
This guide describes the capabilities of the configurable logic blocks (CLBs) available in all Xilinx® 7 series FPGA. |
ver 1.3 | 2.27 MB |
| UG479：7 Series FPGA DSP48E1 Slice User Guide。
This guide describes the DSP48E1 slice in 7 Series FPGA and includes configuration examples. |
ver 1.3 | 1.92 MB |
| UG480：7 Series FPGA XADC User Guide。
This guide serves as a technical reference describing the Xilinx® 7 series FPGA XADC, a dual 12-bit, 1 MSPS analog-to-digital converter with on-chip sensors. Design file for UG480 |
ver 1.1 | 2.47 MB |
| UG483：7 Series FPGA PCB Design and Pin Planning Guide。
This guide provides information on PCB design and pin planning for 7 series FPGA, with a focus on strategies for making design decisions at the PCB and interface level. |
ver 1.4 | 3.32 MB |
| UG429：7 Series FPGA Migration Methodology Guide。
This document describes how to migrate designs utilizing prior FPGA architectures to 7 series FPGA for improved density (cost), performance, and power. |
ver 1.0 | 579 KB |
| UG586：7 Series FPGA Memory Interface Solutions User Guide (AXI)。
This User Guide provides information about using, customizing, and simulating LogiCORE™ IP DDR3 and DDR2 SDRAM, RLDRAM II, and QDRII+ SRAM memory interface cores for 7 series FPGA. This document also describes an optional AXI4 interface. |
ver 1.4 | 11.3 MB |
| 描述 | 修改 | 大小 |
| EN211： Virtex-7 FPGA XC7VX1140T CES9937 Errata。 Errata for the Virtex®-7 FPGA XC7VX1140T CES9937 devices. | ver 1.0 | 157 KB |
| EN180：Virtex-7 FPGA XC7V2000T CES9937 Errata。 Errata for the Virtex®-7 FPGA CES9937 devices. | ver 1.3 | 144 KB |
| EN195：Virtex-7 FPGA XC7VX485T CES9900 Errata。 Errata for the Virtex®-7 FPGA XC7VX485T CES9900 devices. | ver 1.0 | 122 KB |
| EN171：Kintex-7 FPGA XC7K325T CES9937。Errata： Errata for the Kintex™-7 FPGA XC7K325T CES9937 devices. | ver 1.6 | 154 KB |
| EN183：Kintex-7 FPGA CES Errata。Errata for the Kintex™-7 FPGA CES devices. | ver 1.1 | 135 KB |
| EN193：Virtex-7 FPGA XC7VX485T CES9925 Errata 。 Errata for the Virtex®-7 FPGA XC7VX485T CES9925 Errata devices. | ver 1.0 | 187 KB |
| EN179：Kintex-7 FPGA XC7K480T CES9937 Errata。 Errata for the Kintex™-7 FPGA XC7K480T CES9937 devices. | ver 1.3 | 135 KB |
| EN190：Kintex-7 FPGA CES9925 Errata。 Errata for the Kintex™-7 FPGA CES9925 devices. | ver 1.2 | 139 KB |
| EN192：Virtex-7 FPGA CES Errata。 Errata for the Virtex®-7 FPGA CES devices. | ver 1.0 | 133 KB |
| EN172：Virtex-7 FPGA XC7VX485T CES9937 Errata。 Errata for the Virtex®-7 FPGA XC7VX485T CES9937 devices. | ver 1.5 | 140 KB |
| 描述 | 修改 | 大小 |
| XAPP497：Bitstream Identification with USR_ACCESS Application Note。
The USR_ACCESS register, present in the Virtex®-5, Virtex-6, and all 7 series FPGA, provides the ability to embed version information into a 32-bit fabric-accessible register at the bitstream generation phase, allowing for the best balance of flexibility for the user with minimal impact to the design and implementation time。 |
ver 1.0 | 214 KB |
| 描述 | 修改 | 大小 |
| WP373：Xilinx Redefines Power, Performance, and Design Productivity with Three Innovative 28 nm FPGA Families: Virtex-7, Kintex-7, and Artix-7 Devices | v1.1 | 298 KB |
| WP423：Scaling High-Performance Applications for Low Power and Cost | v1.0 | 680 KB |
| WP389：Lowering Power at 28 nm with Xilinx 7 Series FPGA | v1.1.1 | 1.06 MB |
| WP392：Xilinx Agile Mixed Signal Solutions | v1.0.1 | 562 KB |
| WP249：SPI-4.2 Dynamic Phase Alignment。
This document explains the operation of the SPI-4.2 Dynamic Phase Alignment (DPA) Sink Core for Virtex®-4, Virtex-5, Virtex-6, and 7 series FPGA and provides the guidelines on how to use the SPI-4.2 DPA solution. |
ver 1.3 | 605 KB |
| WP312：Xilinx Next Generation 28 nm FPGA Technology Overview The breakthrough combination of a high-performance, low-power process with architectural innovations makes new 28 nm FPGA well suited for power-sensitive applications, bandwidth-intensive, and ultra-high-end applications. |
ver 1.1 | 614 KB |
| WP370：Reducing Switching Power with Intelligent Clock Gating。 Xilinx delivers the first automated, fine-grain clock-gating solution that can reduce dynamic power by up to 30% for Virtex®-6, Spartan®-6, Kintex™-7 and Virtex-7 FPGA designs. |
ver 1.3 | 395 KB |
| WP374：Partial Reconfiguration of Xilinx FPGA Using ISE Design Suite。 This white paper addresses the flexible partial reconfiguration options when designing with Xilinx® 7 series, Virtex®-6, Virtex-5, and Virtex-4 FPGA. |
ver 1.2 | 377 KB |
| WP383：Achieving High Performance DDR3 Data Rates in Virtex-7 and Kintex-7 FPGA。 This white paper describes various memory interface and controller design challenges and the 7 series FPGA high-performance solution that achieves a 1.866 Gb/s DDR3 data rate for Virtex®-7 and Kintex™-7 FPGA. |
ver 1.1 | 344 KB |
| WP384：PCI Express for the 7 Series FPGA。 Since the introduction of the PCI Express® protocol, Xilinx has been the market leader in FPGA-based PCI Express solutions—from the soft IP FPGA logic-based solutions in the Virtex®-II Pro family, to the first Integrated Block for PCI Express in the Virtex-5 FPGA family, to its continued use in Virtex-6 and Spartan®-6 devices. The 7 series FPGA will include the latest generation Integrated Block for PCI Express within a Xilinx FPGA. This breadth of experience has provided Xilinx the expertise to develop the easiest to use, most feature-rich, and highest performance PCI Express solution available. |
ver 1.0 | 467 KB |
| WP385：Industry’s Highest Bandwidth FPGA Enables World’s First Single-FPGA Solution for 400G Communications Line Cards。 Xilinx is responding to the demand for more bandwidth with two key developments. The first is high-fidelity 28 Gb/s transceiver technology. The second is 28 nm Virtex®-7 HT FPGA that integrate an unprecedented 16 x 28 Gb/s and 72x13.1 Gb/s transceivers with logic, memory, and I/O resources that enable the first silicon device (FPGA orotherwise) to support 400G line cards and the industry’slargest single-FPGA solution for Nx100G line cards. |
ver 1.1 | 623 KB |
| WP393：I/O and Memory Interfacing Features and Benefits in 7 Series Architecture。 This white paper describes how the new I/O structures in the 7 series architecture support the range of performance and functionality challenges needed to address the broad range of application needs. |
ver 1.0 | 694 KB |
