This specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications.

This guide describes the SelectIO™ resources available in all the Virtex®-6 devices.

This guide describes the clocking resources available in all the Virtex®-6 devices, including the MMCM and Clock Buffers.

This guide describes the Virtex®-6 device block RAM and FIFO capabilities.

This guide describes the capabilities of the configurable logic blocks (CLBs) available in all Virtex®-6 devices.

This guide describes the GTX transceivers available in all the Virtex®-6 FPGAs except the XC6VLX760.

This guide describes the GTH transceivers available in the Virtex®-6 HXT FPGAs.

This guide describes the dedicated tri-mode Ethernet media access controller (TEMAC) available in all the Virtex®-6 FPGAs except the XC6VLX760.

This guide describes the function and operation of the Virtex®-6 FPGA Integrated Block for PCI Express®, including how to design, customize, and implement it. This solution supports the legacy TRN interface for the customer user interface.

This guide describes the DSP48E1 slice in Virtex®-6 FPGAs and includes configuration examples.

This guide describes the System Monitor functionality.

The Virtex®-6 FPGA GTX Transceiver Signal Integrity Simulation Kit for Synopsys HSPICE enables signal integrity simulations of a communication link between Virtex-6 FPGA GTX transceivers. This kit includes models of the line driver of the transmitter and the analog front end of the receiver of the GTX transceivers.

This guide describes the Virtex®-6 FPGA GTX Transceiver Signal Integrity Simulation (SIS) Kit for Mentor Graphics HyperLynx.

This guide provides information on PCB design for Virtex®-6 devices, with a focus on strategies for making design decisions at the PCB and the interface level.

EN101: Errata for the Virtex®-6 FPGA LX760, LX550T, LX365T, LX240T, LX195T, LX130T, SX475T, and SX315T devices.

EN142: Errata for the Virtex®-6 FPGA LX, LXT, SXT, and HXT production devices.

EN145: Errata for the Virtex®-6 FPGA HX250T and HX380T CES devices.

EN154: Errata for the Virtex®-6 FPGA -1L speed grade LX75T, LX130T, LX195T, LX240T, LX365T, LX550T, LX760, SX315T, and SX475T devices.

EN157: Errata for the Virtex®-6 FPGA HX255T, HX380T, and HX565T CES devices.

To inform customers of a change to the Humidity Indicator Card (HIC). There is no change to the form, fit, or function.

To inform Xilinx customers of corrections to the described behavior of specific function blocks within the Virtex®-6 FPGA. The affected function blocks include the built-in synchronous FIFO and the input logic registers.

To inform Xilinx customers of changes to the Virtex®-6 FPGA user guide, data sheet and JTAG revision codes.

The ISE® 11.x, 12.x and 13.1 TRCE/Timing Analyzer tools do not correctly analyze certain control signals and address lines of the Virtex®-6 36Kb BRAM (RAMB36E1), 18Kb BRAM (RAMB18E1), and 18Kb FIFO (FIFO18E1) when used in SDP, TDP, or ECC modes, potentially resulting in unreported setup and hold time violations. The unreported violations can result in read and write errors in silicon and are not reported in the unconstrained path report section of the timing report.

This application note describes the implementation of SERDES Framer Interface Level 5 (SFI-5) in a Virtex®-6 XC6VLX240T FPGA.

设计文件:

• xapp882.zip

This application note describes a data integrity controller for partial reconfiguration (PRC) that can be included in any partially reconfigurable FPGA design to process partial bitstreams for data integrity

This application note provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the Virtex®-6 FPGA mixed-mode clock manager (MMCM) through its dynamic reconfiguration port.

设计文件:

• xapp878.zip

This application note describes how to utilize the dedicated deserializer(ISERDES) and serializer (OSERDES) functionalities in Virtex®-6 FPGAs to interface with analog-to-digital converters that have serial low-voltage differential signaling (LVDS) outputs and with digital-to-analog converters that have parallel LVDS inputs.

XAPP1073 - NSEU Mitigation in Avionics Applications。

This application note provides background on NSEUs in SRAM-based FPGAs, mitigation techniques (with a focus on configuration memory) suggested by Xilinx, and an overview of calculating projected failures-in-time (FIT) rates at altitude.

XAPP880 - SFI-4.1 16-Channel SDR Interface with Bus Alignment Using Virtex-6 FPGAs。

设计文件:

• xapp880.zip

This application note uses Virtex®-6 FPGA SelectIO™ technology to perform 4X asynchronous oversampling at 1.25 Gb/s. The oversampling is accomplished using the ISERDESE1 primitive through the mixed-mode clock manager (MMCM) dedicated performance path.

设计文件:

• xapp881.zip

This application note presents a Verilog reference design that has been simulated, synthesized, and verified on hardware using Virtex®-6 FPGAs and QDR II SRAM two-word burst devices.

设计文件:

• IPC-1752 Form

100% Material Declaration Data Sheet FFG1759 Package for Virtex®-6 FPGAs

设计文件:

• IPC-1752 Form

100% Material Declaration Data Sheet

设计文件:

• IPC-1752 Form

100% Material Declaration Data Sheet FFG1156

设计文件:

• IPC-1752 Form

100% Material Declaration Data Sheet FF1156

设计文件:

• IPC-1752 Form

设计文件:

• IPC-1752 Form

This characterization report compares the electrical performance of the Virtex®-6 FPGA GTH transceivers against OIF-CEI-02.0, Common Electrical I/O (CEI)—Electrical and Jitter Interoperability agreements for 6 Gb/s and 11 Gb/s I/O and IEEE Std 802.3ba-2010 Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer specifications.

This protocol compatibility report compares the physical layer (PHY) electrical performance of the Virtex®-6 FPGA GTX transceiver against the Common Public Radio Interface (CPRI) specification, v4.1.

This characterization report compares the electrical performance of the Virtex®-6 FPGA GTX transceiver against the PCI Express® Revision 2.0 specifications published in the PCI Express Base Specification, Revision 2.1 and the PCI Express Card Electromechanical Specification, Revision 2.0.

This protocol characterization summary report compares the electrical performance of the Virtex®-6 FPGA GTX transceiver against the 10 Gb Attachment Unit Interface (XAUI) specifications.

This document explains the operation of the SPI-4.2 Dynamic Phase Alignment (DPA) Sink Core for Virtex®-4, Virtex-5, Virtex-6, and 7 series FPGAs and provides the guidelines on how to use the SPI-4.2 DPA solution.

At 40 and 45 nm process nodes, power has become the primary factor for FPGA selection. Spartan®-6 and Virtex®-6 FPGAs offer lower power, simpler power systems and PCB complexity, better reliability, and lower system cost. This white paper details how Xilinx designed for this new reality in Spartan-6 (45 nm) and Virtex-6 (40 nm) FPGA families, achieving dramatic power reductions over previous generation devices.

This white paper describes the Virtex®-6 FPGA Connectivity Kit (DK-V6-CONN-G) and the Spartan®-6 FPGA Connectivity Kit (DK-S6-CONN-G) that engineers can use to jump-start their connectivity-based designs.

The Virtex®-6 and Spartan®-6 architectures feature flexible internal memory resources that can be configured in a variety of different sizes. This white paper details the available features, illustrating the wide array of memory sizes available and shows the trade-off of using different resources to perform memory functions of different sizes.

ISE® Design Suite v12 is the production-optimized tool suite for Virtex®-6 and Spartan®-6 FPGAs that delivers innovation in three critical areas of FPGA design: power reduction, productivity, and performance.

Xilinx delivers the first automated, fine-grain clock-gating solution that can reduce dynamic power by up to 30% for Virtex®-6, Spartan®-6, Kintex™-7 and Virtex-7 FPGA designs.

Advancements in silicon, software, and IP have proven Xilinx FPGAs to be the ideal solution for accelerating applications on high-performance embedded computers and servers. This white paper describes the various use models for applying FPGAs in High Performance Computing (HPC) systems.

The AXI4 specification represents a major evolutionary step in interconnect technology for on-chip system design. The value of the AXI4 interconnect has many facets, beginning with an immediate gain in productivity derived from a unified IP interconnect standard that supplants legacy and custom interconnect architectures. The three interconnect protocols developed for the AXI4 standard (AXI4, AXI4-Lite, and AXI4-Stream interfaces) provide the flexibility to optimize an FPGA design for performance, throughput, latency, or area.

Xilinx continues to refine the place and route algorithms in each of the ISE® software releases and provides up-to-date information on additional design techniques to help customers optimize routing in their Virtex®-6 FPGA designs, making it easier to reach performance and power design goals and achieve next-generation bandwidth requirements.

The IBIS Algorithmic Modeling Interface (IBIS-AMI) was developed to enable fast, accurate statistical and time-domain simulation of high-speed channels. It combines the ease of use and speed of standard IBIS signal integrity analysis with advanced communications analysis techniques.