SN65LVDS047 具有直通式引脚的四路 LVDS 发送器
The intended application of this device and signaling technique is for point-to-point and multi-drop baseband data transmission over controlled impedance media of approximately 100
SN55LVDS31 SN65LVDM31 SN65LVDS047 SN65LVDS048A SN65LVDS31 SN65LVDS32 SN65LVDS33 SN65LVDS348 SN65LVDS352 SN65LVDS390 SN65LVDS391 SN75LVDS31
Input Signal
LVTTL
LVCMOS
LVTTL
LVDS
LVTTL
LVDS
CMOS, ECL, LVCMOS, LVDS, LVECL, LVPECL, PECL
CMOS, ECL, LVCMOS, LVDS, LVECL, LVPECL, PECL
CMOS, ECL, LVCMOS, LVDS, LVECL, LVPECL, PECL
LVDS
LVTTL
Output Signal
LVDS
LVDM
LVDS
LVTTL
LVDS
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVDS
LVTTL
No. of Rx
4
4
4
4
4
4
No. of Tx
4
4
4
4
4
4
4
Signaling Rate(Mbps)
400
150
400
400
400
100
400
340
560
630
630
155
Supply Voltage(s)(V)
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
ICC(Max)(mA)
35
40
26
15
35
18
23
20
20
18
26
35
Rx tpd(Typ)(ns)
2.9
2.3
4
4
4
2.6
Tx tpd(Typ)(ns)
1.7
2.3
1.8
1.7
1.7
Part-to-Part Skew(Max)(ps)
1000
1000
1000
800
1000
1000
1000
1000
1500
1000
Pin/Package
16CDIP, 16CFP, 20LCCC
16SOIC
16SOIC, 16TSSOP
16SOIC, 16TSSOP
16SO, 16SOIC, 16TSSOP
16SO, 16SOIC, 16TSSOP
16SOIC, 16TSSOP
16SOIC, 16TSSOP
24TSSOP
16SOIC, 16TSSOP
16SOIC, 16TSSOP
16SOIC, 16TSSOP
Operating Temperature Range(°C)
-55 to 125
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
ESD HBM(kV)
8
12
8
10
8
8
15
15
15
15
Approx. Price (US$)
1.50 | 1ku
1.85 | 1ku
1.30 | 1ku
1.30 | 1ku
1.30 | 1ku
1.20 | 1ku
1.65 | 1ku
2.90 | 1ku
1.20 | 1ku
1.20 | 1ku
1.30 | 1ku
SN65LVDS047 特性
>400 Mbps (200 MHz) Signaling Rates
Flow-Through Pinout Simplifies PCB Layout
300 ps Maximum Differential Skew
Propagation Delay Times 1.8 ns (Typical)
3.3 V Power Supply Design
±350 mV Differential Signaling
High Impedance on LVDS Outputs on Power Down
Conforms to TIA/EIA-644 LVDS Standard
Industrial Operating Temperature Range (–40°C to 85°C)
Available in SOIC and TSSOP Packages
SN65LVDS047 芯片订购指南
器件
状态
温度
价格
封装 | 引脚
封装数量 | 封装载体
丝印标记
SN65LVDS047D
ACTIVE
-40 to 85
1.55 | 1ku
SOIC (D) | 16 40 | TUBE
SN65LVDS047DG4
ACTIVE
-40 to 85
1.55 | 1ku
SOIC (D) | 16 40 | TUBE
SN65LVDS047DR
ACTIVE
-40 to 85
1.30 | 1ku
SOIC (D) | 16 2500 | LARGE T&R
SN65LVDS047DRG4
ACTIVE
-40 to 85
1.30 | 1ku
SOIC (D) | 16 2500 | LARGE T&R
SN65LVDS047PW
ACTIVE
-40 to 85
1.55 | 1ku
TSSOP (PW) | 16 90 | TUBE
SN65LVDS047PWG4
ACTIVE
-40 to 85
1.55 | 1ku
TSSOP (PW) | 16 90 | TUBE
SN65LVDS047PWR
ACTIVE
-40 to 85
1.30 | 1ku
TSSOP (PW) | 16 2000 | LARGE T&R
SN65LVDS047PWRG4
ACTIVE
-40 to 85
1.30 | 1ku
TSSOP (PW) | 16 2000 | LARGE T&R
SN65LVDS047 质量与无铅数据
器件
环保计划*
铅/焊球涂层
MSL 等级/回流焊峰
环保信息与无铅 (Pb-free)
DPPM / MTBF / FIT 率
SN65LVDS047D
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS047D
SN65LVDS047D
SN65LVDS047DG4
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS047DG4 SN65LVDS047DG4
SN65LVDS047DR
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS047DR
SN65LVDS047DR
SN65LVDS047DRG4
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS047DRG4 SN65LVDS047DRG4
SN65LVDS047PW
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS047PW
SN65LVDS047PW
SN65LVDS047PWG4
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS047PWG4 SN65LVDS047PWG4
SN65LVDS047PWR
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS047PWR
SN65LVDS047PWR
SN65LVDS047PWRG4
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS047PWRG4 SN65LVDS047PWRG4
SN65LVDS047 应用技术支持与电子电路设计开发资源下载
SN65LVDS047 数据资料 dataSheet 下载 .PDF TI 德州仪器LVDS PHYs选型与价格 . xls 所选封装材料的热学和电学性质 (PDF 645 KB)使用数字隔离器设计隔离式 I2C 总线接口 (zhct119.PDF, 339 KB)1Q 2011 Issue Analog Applications Journal (slyt399.PDF, 964 KB)接口选择指南 (Rev. D) (PDF 2994 KB)Signaling Rate vs. Distance for Differential Buffers (PDF 420 KB)Q1 2009 Issue Analog Applications Journal (slyt319.PDF, 1.39 MB)Isolated RS-485 Reference Design (PDF 80 KB)无铅组件涂层的保存期评估 (PDF 1305 KB)Analog Signal Chain Guide (8.62 MB)Industrial Interface IC Solutions (101 KB)
The SN65LVDS047 is a quad differential line driver that implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the four current-mode drivers will deliver a minimum differential output voltage magnitude of 247 mV into a 100-
load when enabled.
