SN65LVDS348 具有 -2 至 4.4V 共模范围的四路 LVDS 接收器
SN55LVDS31 SN65LVDM31 SN65LVDS047 SN65LVDS048A SN65LVDS31 SN65LVDS32 SN65LVDS33 SN65LVDS348 SN65LVDS352 SN65LVDS390 SN65LVDS391 SN75LVDS31
Input Signal
LVTTL
LVCMOS
LVTTL
LVDS
LVTTL
LVDS
CMOS, ECL, LVCMOS, LVDS, LVECL, LVPECL, PECL
CMOS, ECL, LVCMOS, LVDS, LVECL, LVPECL, PECL
CMOS, ECL, LVCMOS, LVDS, LVECL, LVPECL, PECL
LVDS
LVTTL
Output Signal
LVDS
LVDM
LVDS
LVTTL
LVDS
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVDS
LVTTL
No. of Rx
4
4
4
4
4
4
No. of Tx
4
4
4
4
4
4
4
Signaling Rate(Mbps)
400
150
400
400
400
100
400
340
560
630
630
155
Supply Voltage(s)(V)
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
ICC(Max)(mA)
35
40
26
15
35
18
23
20
20
18
26
35
Rx tpd(Typ)(ns)
2.9
2.3
4
4
4
2.6
Tx tpd(Typ)(ns)
1.7
2.3
1.8
1.7
1.7
Part-to-Part Skew(Max)(ps)
1000
1000
1000
800
1000
1000
1000
1000
1500
1000
Pin/Package
16CDIP, 16CFP, 20LCCC
16SOIC
16SOIC, 16TSSOP
16SOIC, 16TSSOP
16SO, 16SOIC, 16TSSOP
16SO, 16SOIC, 16TSSOP
16SOIC, 16TSSOP
16SOIC, 16TSSOP
24TSSOP
16SOIC, 16TSSOP
16SOIC, 16TSSOP
16SOIC, 16TSSOP
Operating Temperature Range(°C)
-55 to 125
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
ESD HBM(kV)
8
12
8
10
8
8
15
15
15
15
Approx. Price (US$)
1.50 | 1ku
1.85 | 1ku
1.30 | 1ku
1.30 | 1ku
1.30 | 1ku
1.20 | 1ku
1.65 | 1ku
2.90 | 1ku
1.20 | 1ku
1.20 | 1ku
1.30 | 1ku
SN65LVDS348 特性
Meets or Exceeds the Requirements of ANSI TIA/EIA-644A Standard
Single-Channel Signaling Rates1 up to 560 Mbps
–4 V to 5 V Common-Mode Input Voltage Range
Flow-Through Architecture
Active Failsafe Assures a High-level Output When an Input Signal Is not Present
SN65LVDS348 Provides a Wide Common-Mode Range Replacement for the SN65LVDS048A or the DS90LV048A
APPLICATIONS
Logic Level Translator
Point-to-Point Baseband Data Transmission Over 100- ECL/PECL-to-LVTTL Conversion
Wireless Base Stations
Central Office or PABX Switches
SN65LVDS348 芯片订购指南
器件
状态
温度
价格
封装 | 引脚
封装数量 | 封装载体
丝印标记
SN65LVDS348D
ACTIVE
-40 to 85
1.95 | 1ku
SOIC (D) | 16 40 | TUBE
SN65LVDS348DG4
ACTIVE
-40 to 85
1.95 | 1ku
SOIC (D) | 16 40 | TUBE
SN65LVDS348PW
ACTIVE
-40 to 85
1.95 | 1ku
TSSOP (PW) | 16 90 | TUBE
SN65LVDS348PWG4
ACTIVE
-40 to 85
1.95 | 1ku
TSSOP (PW) | 16 90 | TUBE
SN65LVDS348PWR
ACTIVE
-40 to 85
1.65 | 1ku
TSSOP (PW) | 16 2000 | LARGE T&R
SN65LVDS348PWRG4
ACTIVE
-40 to 85
1.65 | 1ku
TSSOP (PW) | 16 2000 | LARGE T&R
SN65LVDS348 质量与无铅数据
器件
环保计划*
铅/焊球涂层
MSL 等级/回流焊峰
环保信息与无铅 (Pb-free)
DPPM / MTBF / FIT 率
SN65LVDS348D
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS348D
SN65LVDS348D
SN65LVDS348DG4
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS348DG4 SN65LVDS348DG4
SN65LVDS348PW
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS348PW
SN65LVDS348PW
SN65LVDS348PWG4
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS348PWG4 SN65LVDS348PWG4
SN65LVDS348PWR
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS348PWR
SN65LVDS348PWR
SN65LVDS348PWRG4
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS348PWRG4 SN65LVDS348PWRG4
SN65LVDS348 应用技术支持与电子电路设计开发资源下载
SN65LVDS348 数据资料 dataSheet 下载 .PDF TI 德州仪器LVDS PHYs选型与价格 . xls 所选封装材料的热学和电学性质 (PDF 645 KB)使用数字隔离器设计隔离式 I2C 总线接口 (zhct119.PDF, 339 KB)1Q 2011 Issue Analog Applications Journal (slyt399.PDF, 964 KB)接口选择指南 (Rev. D) (PDF 2994 KB)Signaling Rate vs. Distance for Differential Buffers (PDF 420 KB)Q1 2009 Issue Analog Applications Journal (slyt319.PDF, 1.39 MB)Isolated RS-485 Reference Design (PDF 80 KB)无铅组件涂层的保存期评估 (PDF 1305 KB)Analog Signal Chain Guide (8.62 MB)Industrial Interface IC Solutions (101 KB)
The SN65LVDS348, SN65LVDT348, SN65LVDS352, and SN65LVDT352 are high-speed, quadruple differential receivers with a wide common-mode input voltage range. This allows receipt of TIA/EIA-644 signals with up to 3-V of ground noise or a variety of differential and single-ended logic levels. The ’348 is in a 16-pin package to match the industry-standard footprint of the DS90LV048. The ’352 adds two additional VCC and GND pins in a 24-pin package to provide higher data transfer rates with multiple receivers in operation. All offer a flow-through architecture with all inputs on one side and outputs on the other to ease board layout and reduce crosstalk between receivers. LVDT versions of both integrate a 110-
line termination resistor.
