对应所有封装类型的以逗号分隔的 ASCII 文本文件和 Excel 电子数据表

本白皮书介绍了一种大家很少注意到的设计技巧。该技巧可以让您的 FPGA 设计尺寸和性能发生重大变化。FPGA 触发器上的控制信号具有优先权。如果您能学会编写符合优先权要求的代码，结果就很有利了。为了解释重点，本白皮书提供了一些简单的 VHDL 和 Verilog 实例。

本技术文档提供了 MATLAB 语言子集的简要介绍，包括运算子以及面向 Xilinx FPGA 用于算法综合的 AccelDSP™ 综合工具支持的内置和工具箱功能。

Operating logic at a higher rate than the processing rate allows operations to be achieved sequentially. As with a processor, logic is timeshared over multiple clock cycles. Memory holds values not being used on a given clock cycle. The FPGA can be considered to be a three-dimensional volume to be filled. "Performance + Time = Memory" is a strange formula, but when understood, it can often result in significantly lower cost implementations with Xilinx devices.

This white paper considers a variety of ways in which multiplexers can be implemented within Xilinx FPGA devices, including some alternative techniques that can lead to more efficient and lower cost implementations.

Applying a global reset to your FPGA designs is not a very good idea and should be avoided. This is a controversial issue, so this white paper looks at the reasons why such a design policy should be considered.

FPGAs can be configured with test applications during the development and production test stage. This white paper explores efficient options to help in product development and accelerate testing on the production line.

Using Xilinx Spartan™-3E and Spartan-3A FPGAs, a National Semiconductor PHY, and a Xilinx video processing stack provides a very cost-effective and flexible approach to the challenges of multi-rate broadcast.

本白皮书介绍了 Spartan®-3 FPGA 如何能够将总系统成本降低 50%（相对于竞争 FPGA）。

本白皮书提供了实例，用于帮助您了解 SRL16E 的性能和使用方法，以便提升设计性能并将设计成本降低一个数量级。

This white paper describes the steps necessary to analyze your design's power requirements using the Xilinx® Power Estimator.

This application note describes a cost-optimized copy protection scheme that helps protect an FPGA against cloning. The design leverages an external secure serial EEPROM. The included reference design uses an optimized PicoBlaze™ 8-bit microcontroller. This application note provides a hardware design with associated PicoBlaze software code. The code loads a secret key into the secure EEPROM and authenticates the user system with the secure EEPROM.

设计文件:

• xapp780.zip

This application note describes solutions to receive large-swing signals by design. In one solution (and in the general case of severe positive and/or negative overshoot), parasitic leakage current between User I/Os in differential pin pairs may occur, even though the User I/O pins are configured with single-ended I/O standards. This application note addresses parasitic leakage current behavior.

This application note targets Spartan®-3E/3A devices in applications that require 4-bit or 5-bit receive data bus widths and operate at rates up to 666 Mbps per line with a clock at 1/7th the bit rate. This type of interface is commonly used in flat panel displays and automotive applications.

设计文件:

• xapp485.zip

This application note targets Spartan™-3E devices in applications that require 4-bit or 5-bit transmit data bus widths and operate at rates up to 666 Mbps per line with a forwarded clock at 1/7th the bit rate. This type of interface is commonly used in flat panel displays and automotive applications.

设计文件:

• xapp486.zip

This application note describes the implementation of six circuits necessary to perform commonly used conversions between various chroma formats. It is accompanied by reference designs which include Generic RTL VHDL code.

设计文件:

• xapp932.zip

The block memories in the Virtex®-II architecture are capable of supporting data bus widths of up to 36-bits. A self-addressing FIFO reference design uses these block memories to store both data and address information in a single memory location. This application note describes FIFO designs where no external counters are required. Only flag and status information logic is used. The resulting FIFOs are not fast (around 150 MHz). Their advantage is in using only one clock load. In addition, the status mechanism is very simple making FIFOs are more suitable for data throttling in continuous data systems instead of the full or empty detection required in frame-based data systems.

设计文件:

• xapp291.zip

This application note describes the implementation of an RGB color space to a YCbCr color space conversion circuit necessary in many video designs.

设计文件:

• xapp930.zip

本应用指南讨论了针对 Xilinx 复杂可编程逻辑器件 (CPLD)、现场可编程门阵列 (FPGA) 和 PROM 系列的配置和编程选项，并说明了一些用于每个系列的最普遍的配置方法。本技术文档包括针对 Virtex Spartan、XPLA3、XC9500、XC17S00 和 XC18V00 系列的配置快速入门指南。

本应用指南为用户提供适用于 Xilinx 器件的 SVF 和 XSVF 文件格式的总体理解。这是基于对 IEEE STD 1149.1 (JTAG) 有一定了解的假设之上。了解在嵌入式编程应用中利用串行矢量格式 (SVF) 和 Xilinx 串行矢量格式 (XSVF) 文件的信息，请参照 Xilinx 应用指南 XAPP058。

本应用指南描述了二维列序滤波器的实现。该参考设计包括了有效排序算法的 RTL VHDL 实现。

设计文件:

• xapp953.zip

本应用指南描述了通过以太网端口进行远程 FPGA 重新配置的方法。

设计文件:

• xapp441_designfiles.zip
• xapp441_designfiles.zip

该应用指南描述了Spartan™-3E系列内的串行外设接口（SPI）配置模式。

必须控制触地反弹以确保高性能 FPGA 器件的正常运行。 要特别注意在 PCB 布局过程中将板级感应系数最小化。 该技术文档描述了有助于确保设计满足接收来自于 FPGA 的信号的器件对输入负脉冲信号和逻辑低电压要求的几种计算。

设计文件:

• xapp689.zip

This application note provides a Xilinx FPGA solution to two-dimensional filtering with a parameterized VHDL reference design. This product is not recommended for new designs.

设计文件:

• xapp933.zip

本应用指南描述了如何将 Spartan™-II 和 Virtex™ 系列内现有的双端口块存储器用作四端口存储器。这实际上涉及了如何折中数据存取时间（减半）和功能（加倍）。块存储器的总带宽每秒保持同样的比特数。

设计文件:

• xapp228.zip

XAPP482 描述了一种 MicroBlaze™ 系统，该系统把软件代码、用户数据、和配置数据存储在非易失性 Platform Flash PROM 内，简化了系统设计并降低了成本。它提供了执行过程中使用的便携式硬件设计，软件设计和附加脚本功能。

设计文件:

• xapp482.zip

最新英文版本

J 驱动编程引擎为 IEEE 标准 1532 可编程逻辑器件 (PLD) 提供了迅速、直接地在系统配置 (ISC) 支持。配置一个在系统器件，编程引擎利用来自于 1532 边界扫描描述语言 (BSDL) 的配置算法信息，来使用通过 IEEE 标准 1149.1 测试访问端口 (TAP) 传输的来自于 1532 数据文件的配置数据。J 驱动可执行源代码和编程示例也可在 Xilinx 网站的下载文件包中得到。J 驱动编程引擎可以用于以下 Xilinx 系列：CoolRunner-II CPLD、XC9500/XL/XV CPLD、Spartan-3 系列 FPGA、Virtex-II 系列 FPGA 以及更新系列的 FPGA。

设计文件:

• xapp500.zip

Verification is an integral part of any FPGA design project. Many older verification models are no longer appropriate to the new multimillion-gate FPGAs, and more modern methods must be brought to bear if verification is to positively affect product time to market. The methodologies used for designing and implementing a good verification plan are discussed in detail, in the context of a real-world verification case study.

The PCI™ Local Bus Specification defines a number of power and reset requirements. When considered in an FPGA implementation, these create several challenges that must be addressed for long term reliability and broad interoperability. This application note applies to compliant PCI applications using Spartan™-3 Generation FPGAs, and is relevant to other Xilinx FPGA families, as well as related PCI applications.

设计文件:

• xapp457.zip

PCI 指标为实现 33 MHz 和 66 MHz 操作定义了两个 I/O 时序预算。 在嵌入式设计中，定制时序预算可以：• 通过使用较经济的器件来降低系统总成本 • 实现比指标允许值更高的数据传输速率 • 为总线添加更多负载，来适应附加器件和连接器 • 增加总线的物理长度，来满足新型总线拓扑。本应用指南介绍的信息适用于任何采用 Xilinx FPGA 器件的嵌入式 PCI 实现。

关于本应用指南的最新版本，请参见用户指南 UG331，Spartan™-3 系列 FPGA 用户指南中的多路复用器章节。

设计文件:

• xapp466_vhdl.zip
• xapp466_verilog.zip

Describes how Extended Spartan®-3A family and Spartan-3E FPGAs work in spread-spectrum applications.

This application note discusses using the provided Memory Endpoint Test (MET) demonstration driver to exercise the Programmed Input/Output (PIO) design that is delivered with the Endpoint Block Plus Wrapper, Endpoint, and Endpoint PIPE for PCI Express® Xilinx solutions.

设计文件:

• xapp1022.zip

This application note describes how to interface 3.3V differential Low-Voltage Positive Emitter Coupled Logic (LVPECL) drivers with Xilinx® 2.5V differential receivers, including Virtex®-II Pro, Virtex-II Pro X, Virtex-4, Virtex-5, Spartan®-3E, and Spartan-3 FPGA 2.5V LVPECL and Low Voltage Differential Signaling (LVDS). Several interface modifications are presented with supporting IBIS simulation results.

This application note contains guidelines on reflow soldering, inspection, and rework process for Pb-free packages.

The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.

设计文件:

• xapp058.zip

In embedded systems, designers can reduce component count and increase flexibility by using a microprocessor to configure an FPGA. C code illustrates the use of either Slave Serial or SelectMAP mode. CPLD design files illustrate a synchronous interface between processor and FPGA.

设计文件:

• xapp502.zip

先前在本通知的早期修订版中描述的所有勘误项均作为 0 级生产器件而集成到 Spartan™-3E 数据手册中。 了解更多信息，请参照数据手册中的“生产分级”部分。

先前在本通知的早期修订版中描述的所有勘误项均作为 0 级生产器件而集成到 Spartan™-3E 数据手册中。 了解更多信息，请参照数据手册中的“生产分级”部分。

See “Production Stepping” section in the data sheet for additional information.

了解更多信息，请参照数据手册中的“生产分级”部分。

See “Production Stepping” section in the data sheet for additional information.

Describes the configuration features of the Spartan®-3 Generation FPGAs. Includes the Spartan-3A, Spartan-3AN, Spartan-3A DSP, Spartan-3E, and Spartan-3 FPGA families.

FG320 - Material Declaration Data Sheet (Standard Fine-Pitch BGA)

100% Material Declaration Data Sheet for VQ100 package

VQG100 - Material Declaration Data Sheet (Pb-free VQFP)

User guide for getting started with the MicroBlaze™ Development Kit using the Spartan™-3E 1600E.

设计文件:

• ug258.zip

This user guide describes the components and operation of the Spartan®-3E FPGA Starter Kit Board. The Starter Kit provides a low-cost, easy-to-use development and evaluation platform for Spartan-3E FPGA designs.

设计文件:

• s3e_starter_gerbers.pdf
• 参考设计：http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm
• S3E_Starter_Schematic.pdf
• S3E_SK_BOM_RevD.xls