本白皮书介绍了一种大家很少注意到的设计技巧。该技巧可以让您的 FPGA 设计尺寸和性能发生重大变化。FPGA 触发器上的控制信号具有优先权。如果您能学会编写符合优先权要求的代码，结果就很有利了。为了解释重点，本白皮书提供了一些简单的 VHDL 和 Verilog 实例。

本白皮书确定了首要的设计安全威胁，研究了高级安全选项，并介绍了 Xilinx 的新型低成本 Spartan™-3A、Spartan-3AN 和 Spartan-3A DSP FPGA 是如何保护您的产品与利益。

最新英文版本

本白皮书确定了首要的设计安全威胁，研究了基本的安全级别，并介绍了 Xilinx 的新型低成本 Spartan™-3A、Spartan-3AN 和 Spartan-3A DSP FPGA 是如何保护您的产品和利益。

最新英文版本

本技术文档提供了 MATLAB 语言子集的简要介绍，包括运算子以及面向 Xilinx FPGA 用于算法综合的 AccelDSP™ 综合工具支持的内置和工具箱功能。

Operating logic at a higher rate than the processing rate allows operations to be achieved sequentially. As with a processor, logic is timeshared over multiple clock cycles. Memory holds values not being used on a given clock cycle. The FPGA can be considered to be a three-dimensional volume to be filled. "Performance + Time = Memory" is a strange formula, but when understood, it can often result in significantly lower cost implementations with Xilinx devices.

This white paper considers a variety of ways in which multiplexers can be implemented within Xilinx FPGA devices, including some alternative techniques that can lead to more efficient and lower cost implementations.

Applying a global reset to your FPGA designs is not a very good idea and should be avoided. This is a controversial issue, so this white paper looks at the reasons why such a design policy should be considered.

FPGAs can be configured with test applications during the development and production test stage. This white paper explores efficient options to help in product development and accelerate testing on the production line.

Using Xilinx Spartan™-3E and Spartan-3A FPGAs, a National Semiconductor PHY, and a Xilinx video processing stack provides a very cost-effective and flexible approach to the challenges of multi-rate broadcast.

本白皮书介绍了 Spartan®-3 FPGA 如何能够将总系统成本降低 50%（相对于竞争 FPGA）。

本白皮书介绍了扩展专用乘法器的自然位宽功能以便充分利用整个 FPGA 资源的方法。

本白皮书提供了实例，用于帮助您了解 SRL16E 的性能和使用方法，以便提升设计性能并将设计成本降低一个数量级。

This white paper describes the steps necessary to analyze your design's power requirements using the Xilinx® Power Estimator.

Comma-delimited ASCII text files and Excel footprints for each package type.

Excel file to calculate DFS output jitter based on input and output clock frequencies. Applies to Spartan®-3A, Spartan-3AN, and Spartan-3A DSP platforms.

This document introduces the Extended Spartan®-3A family of FPGAs. It provides features, a device summary, functional overview, packaging options, and ordering information for the device family.

Spartan®-3A FPGA Family Data Sheet, including Overview, Specifications, and Pinouts. See the Spartan-3 Generation User Guides for additional information.

Xilinx 正在世界各地的各个内部仓库中实施仓库管理系统 (WMS)。因此，自 2007 年 8 月起，许可证牌号 (LPN)，即唯一跟踪号码，会标示在标签上。产品的形状、尺寸或功能没有变化。

To inform customers of a change to the Humidity Indicator Card (HIC). There is no change to the form, fit, or function.

The purpose of this Quality Alert is to communicate that the Non-continuous Slave Parallel (SelectMAP) or ICAP_SPARTAN3A data loading via de-asserting CSI_B does not function as expected, and is not a supported feature of these devices.

This notice is to announce the standardization of remaining Spartan®-3A devices to the current 2-layer substrate for the FT256 and FTG256 packages.

设计文件:

• Qualification Report for XCN08014
• FAQ for XCN08014

To communicate the addition of new supply sources for wire bond BGA package core and prepreg material for Spartan®/-XL/-II/-IIE/-3/-3E/-3A/-3AN/-3ADSP/-6, XC95XXX, XC95XXXXL, Virtex®, Virtex®-E, Virtex®-II/-ll Pro, and CoolRunner™ and CoolRunner™-II product.

本用户指南介绍了 Spartan™-3A/3AN 入门套件板修订版 D 的元件和操作方法。入门套件提供了用于 Spartan-3A/3AN FPGA 设计的低成本、简便易用型开发和评估平台。

设计文件:

• reference_designs.htm

This guide provides information about how to use the Video Starter Kit (VSK) to begin experimenting with video processing using the Spartan®-3A DSP family of FPGAs.

本用户指南介绍了Spartan™-3A FPGA 入门套件板修订版C.了解修订版 D 板方面的信息，请参见 UG334。

设计文件:

• reference_designs.htm
• 参考设计：http://china.xilinx.com/products/boards/s3astarter/reference_designs.htm

Spartan™-3A/3AN FPGA 入门套件板原理图。

设计文件:

• s3astarter_bom.xls

Spartan-3A 和 Spartan-3AN 入门套件板的 Gerber 板布局图（PDF 格式）

Describes the configuration features of the Spartan®-3 Generation FPGAs. Includes the Spartan-3A, Spartan-3AN, Spartan-3A DSP, Spartan-3E, and Spartan-3 FPGA families.

This application note targets Spartan®-3E/3A devices in applications that require 4-bit or 5-bit receive data bus widths and operate at rates up to 666 Mbps per line with a clock at 1/7th the bit rate. This type of interface is commonly used in flat panel displays and automotive applications.

设计文件:

• xapp485.zip

This application note describes solutions to receive large-swing signals by design. In one solution (and in the general case of severe positive and/or negative overshoot), parasitic leakage current between User I/Os in differential pin pairs may occur, even though the User I/O pins are configured with single-ended I/O standards. This application note addresses parasitic leakage current behavior.

This application note targets Spartan™-3E devices in applications that require 4-bit or 5-bit transmit data bus widths and operate at rates up to 666 Mbps per line with a forwarded clock at 1/7th the bit rate. This type of interface is commonly used in flat panel displays and automotive applications.

设计文件:

• xapp486.zip

The block memories in the Virtex®-II architecture are capable of supporting data bus widths of up to 36-bits. A self-addressing FIFO reference design uses these block memories to store both data and address information in a single memory location. This application note describes FIFO designs where no external counters are required. Only flag and status information logic is used. The resulting FIFOs are not fast (around 150 MHz). Their advantage is in using only one clock load. In addition, the status mechanism is very simple making FIFOs are more suitable for data throttling in continuous data systems instead of the full or empty detection required in frame-based data systems.

设计文件:

• xapp291.zip

This application note describes how to indirectly program an SPI Serial Flash PROM through the JTAG interface of a Spartan®-3A FPGA using iMPACT 9.1.01i. The hardware setup, software flows for file generation, and programming are also covered.

The PCI™ Local Bus Specification defines a number of power and reset requirements. When considered in an FPGA implementation, these create several challenges that must be addressed for long term reliability and broad interoperability. This application note applies to compliant PCI applications using Spartan™-3 Generation FPGAs, and is relevant to other Xilinx FPGA families, as well as related PCI applications.

设计文件:

• xapp457.zip

J 驱动编程引擎为 IEEE 标准 1532 可编程逻辑器件 (PLD) 提供了迅速、直接地在系统配置 (ISC) 支持。配置一个在系统器件，编程引擎利用来自于 1532 边界扫描描述语言 (BSDL) 的配置算法信息，来使用通过 IEEE 标准 1149.1 测试访问端口 (TAP) 传输的来自于 1532 数据文件的配置数据。J 驱动可执行源代码和编程示例也可在 Xilinx 网站的下载文件包中得到。J 驱动编程引擎可以用于以下 Xilinx 系列：CoolRunner-II CPLD、XC9500/XL/XV CPLD、Spartan-3 系列 FPGA、Virtex-II 系列 FPGA 以及更新系列的 FPGA。

设计文件:

• xapp500.zip

本应用指南描述了 Platform Flash PROM 的功能，它允许用户从多达四种设计修订中进行多重启动或动态重配置。早期中文版

设计文件:

• xapp483.zip

如果不额外使用过孔的话，很难在简单的四层或六层 PCB 上对差分信号，如 LVDS 或 LVPECL 进行布线。 本应用指南说明了 Spartan™-3 FPGA 仅仅在数据路径中包含一个反相器，就能避免额外使用过孔，还可以在无需 PCB 重新设计的情况下，修复 PCB 迹线意外切换的方法。

设计文件:

• xapp491.zip

最新英文版本

XAPP482 描述了一种 MicroBlaze™ 系统，该系统把软件代码、用户数据、和配置数据存储在非易失性 Platform Flash PROM 内，简化了系统设计并降低了成本。它提供了执行过程中使用的便携式硬件设计，软件设计和附加脚本功能。

设计文件:

• xapp482.zip

最新英文版本

Spartan-3A/3AN/3A DSP FPGA 系列提供了一个称为悬挂模式的先进的静态功耗管理功能，它在保留 FPGA 配置数据和保持应用状态的同时降低了 FPGA 功耗。 器件可以按照应用中的要求快速的进入和退出悬挂模式。

PCI 指标为实现 33 MHz 和 66 MHz 操作定义了两个 I/O 时序预算。 在嵌入式设计中，定制时序预算可以：• 通过使用较经济的器件来降低系统总成本 • 实现比指标允许值更高的数据传输速率 • 为总线添加更多负载，来适应附加器件和连接器 • 增加总线的物理长度，来满足新型总线拓扑。本应用指南介绍的信息适用于任何采用 Xilinx FPGA 器件的嵌入式 PCI 实现。

本应用指南描述了如何在 Virtex™-II 和 Spartan™-3 架构内有效实现比 36 位更宽的存储器。 使用的倍频方法类似于 XAPP228 中介绍的四端口存储器的使用方法。 因此，存储器既可用于双端口模式，也可用于单端口模式。

设计文件:

• xapp229.zip

数据恢复是使接收器能够从输入数据流里提取嵌入式时钟数据的机制。 接收器通常从相关数据流里提取该信息，但有时接收器的时钟也用于数据传输。 该应用指南里介绍的电路提供了在 Virtex™-E -7 器件、Spartan™-IIE -6 器件或是 Spartan-3 -4 器件中，数据传输速率达到 160Mb/s 速度；或者在 Virtex-II -5 器件或 Virtex-II Pro™ -6 器件中数据传输速率达到 420Mb/s 时的不完全解决方案。 该解决方案之所以是不完全的，是由于实际上没有时钟被恢复，但是到达的数据全部被提取了。 在 DLL 既可提供新时钟，也可提供另一个转换 90 度的时钟的模式里，速度受限于延迟锁定环 (DLL) 所能接受的最大频率。

设计文件:

• xapp224.zip

本应用指南概述了如何从 Platform Flash PROM 成功配置 Spartan™-3A FPGA。 包括生成 PROM 文件并对其进行编程的硬件要求和软件流程。

本应用指南就在增量设计流程中使用分区技术进行了讨论。 建议将逻辑密度高的模块实例、时序关键通路或时序关键模块实例划归为分区。

最新英文版本

必须控制触地反弹以确保高性能 FPGA 器件的正常运行。 要特别注意在 PCB 布局过程中将板级感应系数最小化。 该技术文档描述了有助于确保设计满足接收来自于 FPGA 的信号的器件对输入负脉冲信号和逻辑低电压要求的几种计算。

设计文件:

• xapp689.zip

本应用指南中讨论的 DDR2-400（200 MHz 时钟）存储器接口源自于 MIG 的默认输出。Xilinx 利用 Spartan™-3A 入门套件上装配的较高的速度级别（-5）在 Spartan-3A FPGA 内对该接口进行了验证。验证结果也适用于 Spartan-3AN 和 Spartan-3A DSP FPGA。

设计文件:

• xapp458.zip

This application note discusses using the provided Memory Endpoint Test (MET) demonstration driver to exercise the Programmed Input/Output (PIO) design that is delivered with the Endpoint Block Plus Wrapper, Endpoint, and Endpoint PIPE for PCI Express® Xilinx solutions.

设计文件:

• xapp1022.zip

本技术文档详细介绍了在针对电信应用的 Virtex™ 和 Spartan™ FPGA 内实现的数字 PLL 的设计方案。对 PLL 的性能和回路稳定性进行了评估。

设计文件:

• xapp868.zip

Describes how Extended Spartan®-3A family and Spartan-3E FPGAs work in spread-spectrum applications.

本应用指南描述了如何将 Spartan™-II 和 Virtex™ 系列内现有的双端口块存储器用作四端口存储器。这实际上涉及了如何折中数据存取时间（减半）和功能（加倍）。块存储器的总带宽每秒保持同样的比特数。

设计文件:

• xapp228.zip

The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.

设计文件:

• xapp058.zip

In embedded systems, designers can reduce component count and increase flexibility by using a microprocessor to configure an FPGA. C code illustrates the use of either Slave Serial or SelectMAP mode. CPLD design files illustrate a synchronous interface between processor and FPGA.

设计文件:

• xapp502.zip

This application note describes a reference design that adds fail-safe mechanisms to the MultiBoot capabilities of the Extended Spartan®-3A family of FPGAs. The reference design configures specific FPGA logic via an initial bitstream that determines which application to load.

设计文件:

• xapp468.zip